Design Project
Resume:
Resume
**,****,****** "sastha nikethan"
Intern Thirunellai village,Thirunellai
Palakkad - 678004
Email id: abjlqs@r.postjobfree.com
Education
****-**** *** ****hna Arts and 70% MSc Electronics and
Science College, Cbe Communication
Systems
2009-2012 C.M.S College Of 63% BSc Electronics And
Science And Commerce, Communication
Cbe Systems
2007-2009 Bharathamatha Hr Sec 70% Class XI & XII
School, Palakkad
2007 Bharathamatha Hr Sec 86% Class X
School, Palakkad
Technical Skills
Languages Verilog, System Verilog, VHDL,C
Others Assembly Level Programming, Oracle Basics
Softwares Xilinx 14.7, NC Sim, Modelsim
Key Interests ASIC Design and Verification, FPGA's
Specialisation UART, SPI, I2C, AHB
Work Experience
Digital Nirvana.Pvt.Ltd - (From 2011 Dec)
Working as a freelancer at Digital Nirvana for English essay evaluation.
Industrial training
TEVATRON TECHNOLOGIES Pvt.Ltd (From July 2014)
Undergoing training as an Intern on VLSI design and verification. Have
done logic design for various protocols like UART, SPI, I2C and AHB using
Verilog and other designs like Arbiter for which verification is also done
using System Verilog.
SINICON private ltd. (In 2011 June)
The training helped in learning and understanding the operation and
processes involved in the production and the operations of automated
products such as water level controllers, power management systems,
security system and also other appliances.
SARK cables private ltd. (In 2010 May)
The fifteen days of training under the supervisors helped in learning about
the various cables manufactured there and the processes included in
manufacturing.
Projects
. December 2014 : AMBA AHB lite Protocol using Single Master Single
Slave in Verilog
The AHB protocol was studied and designed for single master single
slave data transfer in Verilog. The design was done and simulated
using Modelsim 6.4.
. November 2014 : Single Master Multi-Slave I2C Protocol design in
Verilog The design of I2C protocol was done for single master
and multi-slave system after studying the complete working of the
protocol. The design was done and simulated using Modelsim 6.4.
. October 2014 : Serial Peripheral Interface(SPI) Protocol using Verilog
A SPI protocol was designed using Verilog which can
control the speed and mode of transmission. The design was simulated
using Modelsim 6.4.
. September 2014 : Verification of Arbiter design Using System Verilog
The designed Arbiter program using Verilog was undergone
verification in an environment created using System Verilog on NC Sim.
The verification was completed successfully.
. August 2014 : UART with Special Function Registers Using Verilog
In this project a UART is designed with different registers to
control the transmission, receiving and storing of data. The completed
design was simulated in Modelsim 6.4 and ISE Design Suite 14.7.
. Nov 2013 - Mar 2014 : Smart Wireless Home Automation System Using GSM
Technology In
this project the different home appliances are controlled using a PIC
microcontroller. This project also includes various sensors like PIR,
Proximity and Temperature etc. for collecting the input signals and
relays are used to set the output. The system also includes a GSM
module to control the appliances remotely. The objective of the
project is to save power and provide security at home.
Personal Profile
Father's Name : K.Vishwanathan
Occupation : Working as clerk in a private concern
Date of Birth : 06-03-1992
Nationality : Indian
Gender : Male
Martial Status : Single
Permanent Telephone No : 080********
Languages Known : English, Hindi, Malayalam & Tamil
Permanent Address : Vignesh.K.V, 22/172
"Sastha Nikethan"
Thirunellai village,
Palakkad - 678004
E-Mail ID : abjlqs@r.postjobfree.com
abjlqs@r.postjobfree.com
Hobbies
Playing football, cricket and caroms.
Extracurricular Activities
Passionate about singing and dancing.
Strengths
Self-motivated, Determined and Reliable
Weakness
Sensitive, Too helpful.
Declaration
I hereby declare that the particulars furnished above are true and correct
to the best of my knowledge and belief.
Place: Signature
Date:
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