Engineer Design

Kedar Basavaraj

**** ********* ** #** *** Diego CA 92115

abjkx6@r.postjobfree.com

OBJECTIVE

Seeking an Internship/full-time position as an Electrical and Computer

Engineer to work on challenging projects in ASIC/VLSI Design/Verification

related fields.

EDUCATION

San Diego State University, San Diego, CA Fall

'08 - present M.S., Electrical Engineering (GPA

3.64) (Dec '10)

Don Bosco Institute of Technology

July '03 - June '07 B.E., Electronics and

Communication

TECHNICAL SKILL SET

HDL : Verilog and VHDL.

HVL :

SystemVerilog.

Languages

: C, C++,Perl.

Assembly

Languages : 8085 and 8086.

Verification Methodologies :

Coverage Driven Verification.

Test Bench Methodology : VMM from Synopsys.

Synthesis and Simulation Tools : CADENCE, XILINX

ISC,Modelsim,MATLAB.

Platforms :

WINDOWS, UNIX, LINUX.

Softwares : MS Office,

Microsoft Access.

RELAVENT COURSES

VLSI Circuit Design. Digital Signal

Processing

VLSI System Design.

Multimedia Communication Systems.

VLSI ASIC Design.

Embedded Systems.

SystemVerilog. Digital Logic

Design.

WORK EXPERIENCE

ACCENTURE (Software Engineer)

June '07 - July '08

. Worked for the OPTUM-UHG project. UHG is one of the leading Health

Insurance companies in the United States. Our module was incharge of

generating and delivering reports to UHG clients.

. Tools Used : COGNOS Reporting Tool(for generating reports),

MYSQL(for querying SQL statements)

PROJECTS

SystemVerilog Projects

. Implemented a Behavioural RTL Model for a Real Time Clock using

Verilog HDL, architected the class based Verification Environment

using SystemVerilog, and verified the RTL model using SystemVerilog.

EDA Tools used : Modelsim and ISE(Synthesis).

. Implemented a Behavioural RTL Model for a Dual Port Ram using Verilog

HDL, architected the class based verification environment using

SystemVerilog and verified the RTL module using SystemVerilog.

EDA Tools used : Modelsim and ISE(Synthesis).

ASIC Design and System Design Projects

. Designed a 32 point FFT using custom made Adders and Multipliers,

verified it by writing test benches in VHDL and Synthesised it on a

Spartan 3E FPGA . Emphasis was laid on conserving area by reusing the

Adders,Multipliers and 16 Radix-2-Butterflies to calculate the FFT.

EDA Tools used : Modelsim(Simulation) and XILINX ISE(Synthesis).

. Design and Synthesis of a functional RISC Processor, using Harvard

architecture. All stages are pipelined and the functionality of all

the 32 bit instructions are verified by implementing 16 bit Multiply

and Divide subroutines using VHDL.

EDA Tools used : Modelsim(Simulation) and XILINX ISE(Synthesis).

. Design and Synthesis of a Digital Universal Asynchronous Receiver

Transmitter using VHDL.

EDA Tools used : Modelsim(Simulation) and Cadence(Synthesis).

VSLI Circuit Design Projects

. Designed Circuits like Multiplexers, Encoders, Tri-State buffers and

observed propogation delays, Rise time and Fall time.

Simulation Tool : ELDO Spice.

. CMOS circuits(Transistor level simulation), designed and verified the

working of CMOS circuits for basic gates, D-flip flop and parity

check.

Other projects

. Design and construction of a IR controlled Locker Security system by

programming a PIC16F873 micro-controller. The physical model also

consisted of a DTMF decoder to key in the secret passcode for the

locker, IR Transmitter and Receiver to open and close the doors

automatically, Stepper motor for opening and closing the locker, and

Relay Switching.

. Simulation of JPEG image compression scheme in MATLAB that includes

image processing at the transmitter and receiver ends.

. Simulation of MPEG video compression schemes in MATLAB that includes

image processing at transmitter and receiver ends using a couple of

motion vector estimation techniques.

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