Electrical Design

Victor Cordero: M.E. Computer Engineering & M.Sc. Electrical Engineering.

– *******.**@*****.**

*** **** ** **** *** 1710, TX 77840 - (979) 571-

**** *

Objective

To obtain a Full time job position in Computer or Electrical Engineering field where I can put in use

my

graduate school knowledge and past work experience in the VLSI Design

area.

Education

Texas A&M – College Station, expected grad Aug

University TX 2010

Master of Engineering in Computer Engineering (Electrical Eng Dept) GPA

3.3

Graduate level courses

taken:

Advanced Computer Co-Design Embedded Systems Mobile Wireless Network

A(EE

rchitecture s

version)

Phase-Locked Loop Design Statistical Communication Theory Solid State

Devicesdesign for Manufacturability

VLSI Layout Synthesis and Advances in VLSI

Simulation design

of VLSI

Circuits

Test and Diagnostic of Introduction to CAD design Nanobiotechnolog

DSystems

igital Digital y

&

Analog

Phased Arrays

Antennas

University of – Idah Dec

Idaho o 2006

Master of Science in Electrical Engineering, GPA

3.69

MS key

courses: System Engineering

Digital System-on-Chip Parallel

Programming

RF Communication Circuits Thin Film Fabrication Multirate Signal proc

essing

Ad v Wireless Integrated Circuit s & Systems Semiconductor Theory Adaptive Signal

Adv Processing

VLSI Design Statistics for engineers Computer

Architecture CS

Pontific Catholic University of Aug-

Peru 2002

Bachelor of Science Electric al Engineering Top 1%

class

Work Experience

– Aug

IBM TJ Watson Research Labs (Yorktown Heights-New May

York) 2008 2008

IBM Research Intern in the Scalable Server Network & Memory Systems

Area. Phase Change Memory Cell element SPICE modeling for IBM Multi-bit PCM project.-

First

IBM Behavioral PCM SPICE models were written in Synopsys HSPICE,

IBM

POWERSPICE, and Verilog-Analog to allow SPICE electrical simulation under

different Macromodel was aimed to integration in system level design to study

platforms.

the

memory access times, peak currents, power consumption and possible prototype

designs amp technology for PCM. Modeling of PCM thermal evolution models was

for sense

also

implemented in Verilog-A for this

project.

Project was applied as Patent Disclosure to IBM Research Patent office as a

statistical modeling methodology at the end of

PCM

internship.

Collaboration on PCM modeling in Verilog-A for HSPICE simulation continued

during

Dec08-Jan09 for Abe Elfadel. Sonoda's "Compac t Model for PCM based on

Rate

Equations" was fully

implemented.

to ICCAD 2009 “A Two

Paper submitted for review for publication on May

ChangeState

09 Electrothermal Compact Model for Multilevel Memory Cell”. Matlab

Phase- model HSPICE

numerical stabilization and writing of Verilog-AMS code for

implementation.

AMD’s Boston Design Center Co-Op (Boxborough- Aug – Dec

Massachusetts) Design & Implementation Group (Global Circuits subgroup) at 2007 2007

Internship in the Circuit

Advanced Devices

Micro

Inc. Tool developed to study timing correlation of IBM’s EinsTLT to Hspice for AMD’s BSIM

SOI

models. Usage of 2/3 of the commonly used standard cells. Scripts aimed to form part

of

AMD design flow tool tuning

set.

Scripts developed to determine optimal repeaters configuration, in terms of power,

delay,

signal integrity, noise immunity, electro migration, design rules validity for the main

global propagation in AMD’s next core across several corners and

clock

processes.

Writability study for various storage element standard cells in 45nm; Repeaters

library

completion (used for whole design team); Power metrics on standard cells for thermal

tool. gaters spec characterization; Edge rates of s tandard cells study,

Clock

etc.

Directed Research Fall

2009

Texas A&M – Computer Engineering group

University area

Exploratory research on CAD acceleration for analog systems

verification:

Using behavioral closed loop simulations for a full analog system (i.e phased locked

loop),

behavioral waveforms of signals between blocks (i.e PFD+charge pump) are extracted.

The features of these waveforms are extracted (i.e mid rising edge timestamps) to form

key

a ave abstraction. Additional wave parameters are added from the designers input

w

signal specifications of each analog block and a electrical waveform is created.

limit

Each

electrically specified analog block is then simulated (under a much faster) open

loop

method using this generated electrical waveform. To create space covering testing,

a onlinear optimization tool is used that will generate the set of wave parameters used in

n

the

electrical waveform generation. The optimization is looped until a feed-backed

error

function is maximized (i.e charge pump output voltage RMS between behavioral

and using the designer’s

electrical sims) k waveform specs tolerances. The tool flags

bloc if

verified system specifications ’t be met using a particular electrical block.

can

scripts build with PERL, BASH, C++ Ensemble and

HSPICE.

Research Spring

Assistant 2008

Texas A&M – Computer Engineering group

University area ’0 (Design, Automation and Test in Europe) and also at

Paper published in

8 using

DATE

2008- "Clock Distribution Scheme TAU Coplanar Transmission

Lines " that describes a new standing wave oscillator scheme aimed for clock

-Design

propagation

on coplanar transmission lines loop on a silicon die. The clock is transported as

an

oscillatory wave on a pair of conductors. Design for low skew, low power and

high

frequency global clock (8+ GHz). Energy recycling nature of a standing wave

along a

transmission line allows us to keep very high frequencies oscillations along a

conductor power consumption in CMOS 90nm BSim3v models

with low

cards.

– Dec

Research Assistant (prof. Greg Jan

Donohoe) Advanced Microelectronic and Biological Research (CAMBR) at Univ of

2004 2006

Center of

Idaho

Field Programmable Processor Array (FPPA) project: Synthesis and place and route

of core processing element. Synopsys & Cadence EDA tools used. Worked on VHDL

team

writing for this reconfigurable architecture microprocessor, RTL verification and

testing.is a joint NASA/CAMBR project designed as Low-Power, Radiation-Tolerant,

FPPA

VLSI for high-speed processing of streaming spacecraft instrument data. Each

chip

FPPA

contains 16 processing elements units with reconfigurable datapath

connectivity.

Image processing application for FPPA project (MS Thesis): Optimization of the Data

Pathcomputations for the Solar Viewing Interferometer Prototype for the FPPA

architecture. ’s Goddard Space Flight Center and University of

Join project with

NASA

Implementation and improvement Iof NASA image processing control block (very

daho.

high

bandwidth) for adaptive image stabilization of one of NASA’s Satellite prototype

designs aim to study Earth greenhous e gasses. Extensive research done on

which

image

processing, and fixed point mapping of algorithms. Design of new memory access

modes Reconfigurable Memory Modules which work in conjunction with the

for the

FPPA.

Thin Film Inductors Testing circuit designs for the Office of Naval Research project: A

set of high frequency cross coupled oscillators were created to quantify indirectly

capacitance

/ S parameters of Ansoft-HFSS-prototyped thin film inductors designs. Cadence

Virtuoso

layout tools used. Design later used as foundation for proposal to government grant

by a

UI

professor.

DSP application for FPPA: Adaptive signal de-noise LMS system implemented for

fixed

point FPPA architecture. Use of fixed point mathematical models to emulate floating

point.

Extensive MATLAB, Simulink, C++

used.

– Dec

Research/Teaching Aug

Assistant University of 2002 2003

Catholic – Microelectronics

Peru Maintenance and teaching aboratory

L of Cadence tools and Solaris operating system to

students.

(Virtuoso, Buildgates, Silic on Ensemble,

ICFB).

Tools Skills

CAD tools for - Cadence Virtuoso, Synopsys CosmosScope, Synopsys Design

VLSI Cadence Build Gates, Cadence Silicon Ensemble, Synopsys Power Compiler,

Compiler /

Vision,

Synopsys

Scirocco, Synopsys Library Compiler, Mentor Graphics

ModelSim.

CAD high frequency RF – HSPICE, IBM POWERSPICE, Agilent ADS (Advanced

design Design

System), Cadence Analog

environment

Language – Verilog-Analog, PERL, Verilog, VHDL, C++, Java, Assembler for Intel x86,

s Motorola

hc1

1

Math – MATLAB,

tools Simulink Windows, MS Office, CSH, TCSH,

Others - Linux, Cygwin,

BASH

Languages

English and Spanis

h

Employability Status

F-1 Visa student, Co-op CPT and OPT

eligible.

Publications

), “ Clock

Cordero, Vic tor H. and Khatri (Department of ECE, Texas A&M Distribution

Univ Scheme

using Coplanar Transmission ”, “ Design, Automation Test in Europe, 2008. DATE

Lines and '08”,

Munich, Germany, March

2008.

V. Cordero and Khatri (Texas A&M Univ.) “Clock Distribution Scheme using Transmissio

Coplanar 2008 ACM/IEEE International Workshop on Timing Issues in the Specification and n

Lines”,

Digital Synthesis(TAU 2008). Monterey, California February

Systems of

2008Duan, V. Cordero and Khatri,

C. On- Chip Crosstalk Avoidance CODEC IEEE

”Efficient

Transactions on VLSI Systems, accepted in 2008, yet to esign”, in

Dappear

TVLSI. Silva “Design of an ASIC CORE for data

Victor Cordero and ption and decryption using

encry

C. Advanced Encryption Standard NIST

9th IBERCHIP International microelectronic conf. – 200

“ March 3

(Undergrad Thesis

Topic)

“An experimental s ystem for verifying and detecting

Victor Cordero, C. Leon, D. Martin, J

Talledo PCBs ”6th IBERCHIP errors

on using IEEE International microelectronic conf March -

Std.1149.1 2000

References (contact info available upon

request)

Dr. Abe Elfadel, Dr Michele Franceschini, Dr Luis Lastras, Dr Alan – Staff IBM

BivensResearch TJ Watson Research Researchers

– New

IBM

Labs York

– MTS Member of Technical Staff at Global Circuits

Mr. Timothy

Correia(Advanced Micro Devices Inc) Boston Design

Group

AMD

Center

Dr. Gregory – Professor and Department Chair of Computer

Donohoe Science

University of

Idaho

Contact this candidate