Engineer Design

LANE TOMITA *** Terra Mesa

Way

Milpitas, CA

***35

(408)957-

9679

**********@***.***

____________________________________________________________________________

__

OBJECTIVE

A challenging position in ASIC design verification finding problems with

the design, developing the environment, architectual models, and test

strategy.

EXPERIENCE

Consultant Cisco Systems, San Jose, CA

1/2010 - present

Enhanced Vera simulation environment and reference model to support IPSEC

ESP protocol, AES128 CBC and GCM encryption, and HMAC SHA1 and GMAC

authentication algorithms. Created and debugged IPSEC testcases. Updated

base classes to support IPSEC ESP headers, L3 CMD features, IV, and ESP

trailer padding features. Developed new tests, debugged, and fixed current

verification issues with DTLS protocol for minimum frame length errors,

layer 3, 4, and 5 field length errors, layer 3 options, inbound frames with

DTLS length errors after decryption but before authentication, and debugged

regression failures.

Component Design Engineer Intel, Santa Clara, CA

2/08 - 5/09

Lead a team to better structure Specman verification software to allow for

better scalability by being more modular and reusable for both block and

fullchip level simulation environments. Assessed and provided guidance on

writing code that is reusable and scalable by establishing coding

guidelines and rules.

Created and debugged new block level tests for display module. Created

Perl functions to generate assembly tests to enable block level tests to

run at full chip level. Lead a group of 4 to resolve full chip issues with

display checker and simulation termination.

Created checker for memory controller at the full chip level. Created

functional coverage groups and generated and analyzed coverage results.

Created and debugged new LDAT tests. Resolved RINIT, (random

initialization), and removal of channel 0 failures.

Technical Lead Cisco Systems Inc, San Jose, CA

1/01 - 2/08

Responsible for architecture, design, implementation, and testing of a

SystemVerilog register map database, API interface, and control plane

module with driver for register accesses to and from the design.

Successfully led a team of 3 verification engineers to developed a Vera

verification environment, behavioral model, test plan, and

tests for Common Processing Element consisting of a 64 entry fully

associative data cache with ALU, Policer, and WRED functions interfacing

with an external RLDRAM or internal SRAM. Also added functional

coverage for dependency generation checks. Followed up with post silicon

debug support and helping diagnostics with initialization and debug.

Enhanced Specman MAC read/write behavioral model, stimulus generation,

and tests to support embedded DRAM protected by ECC. Also added

assertion checks, ECC error injection, interrupt, and halt support.

Also supported post silicon bringup by debugging failures and writing

diagnostics.

Enhanced Specman environment for the microsequencer processor and CPU

register

access blocks with assertion checks, schmoo tests, and error injection

tests. Followed up with helping out with debug and diagnostics during post

silicon bringup.

Knowledgable in Specman, Vera, PERL, Verilog, CVS, and Clearcase.

Design Verification Engineer Hal Computer Systems, Campbell, CA

7/99 - 1/01

Developed and debugged assembly language testcases for Sparc V9

microprocessor.

Primarily working on load store unit which includes updating the test

plan, creating new tests and generating new biases for random testcase

generation.

Knowledgable in Sparc V9 architecture and UPA architecture.

Member of the Technical Staff Hotrail, San Jose, CA

2/98 - 7/99

Designed SDRAM controller for a shared memory multiprocessor NT system

to support PC100 SDRAMs, DDR, and registered DIMMs.

Member of the Technical Staff Rendition, Sunnyvale, CA

8/97 - 2/98

Responsible for debugging and correcting existing testcases for the

V2100 chip. Built and debugged verilog gate model for context switch

testcases. Experienced in debugging at gate level using Zycad hardware

accelerators.

Design Verification Engineer Hal Computer Systems, Campbell, CA

8/95 - 8/97

Developed PERL and assembly testcases, event checkers, and assertions

for level one cache, unified cache, translation unit, SIU interface, and

UPA

interface. Event checkers and assertions are written in AIDA and Verilog.

Wrote backend

driver to support the cache model. Involved in frequency characterization,

OBP

and kernel debugging during microprocessor bringup. Used logic analyzers,

digital

oscilloscopes, DP/TISIM interface, and GDB to debug problems. Some

experience in

Synopsys's design compiler.

Test Engineer II Advanced Micro Devices, Sunnyvale, CA

7/94 - 8/95

Responsible for bringup and characterization of prototype three volt flash

memory

devices. This incorporated developing the GUI interface down to the low

level functions that interacted with hardware. All low level functions

were

built into a C library which were used by REXX as primitives.

System Test Engineer B Amdahl Corporation, Sunnyvale, CA

7/91 - 7/94

Specialized in I/O processor theory involving IBM ESA/390 and IBM ESCON

architecture. Debugged I/O hardware to component level by creating REXX

programs to

recreate the environment which enabled single cycling up to the root cause

of the

failure. Used tools such as cycle counters, micro-address stops,

microcode, on-line

logic software, scan pages, and ram pages.

As REXX Administrator: wrote REXX programs that stressed I/O processors

by varying voltage margins and frequencies; tracked and diagnosed problems;

implemented corrective action and informed coworkers of updates. Developed

progressive lesson plans and exercises for new members to quickly learn

REXX.

Wrote C code to: calculate the error check code for the unaligned

buffer, channel store, channel manager working store, and aligned buffer;

locate the

problem chip based on the syndrome; identify the chip for replacement based

on

microword parity error; display diagrams for ram bit slicing, syndrome

mapping, physical

layout of optical and parallel channel cards and calculate the channel

number.

Associate Test Engineer KLA Instruments, San Jose, CA

7/90 - 7/91

Wrote diagnostics in C from a DOS platform for ASIC image processor

boards. This involved a new test strategy for complete testing of the

feature

counter, feature ram, 8 registers, feature priority circuitry, and kernel

ram. This

included new test patterns. Wrote assembly code for the 8031

microprocessor to

exercise the illumination power supply for lamp intensity, power on

failure, driver

failure, and excessive current. These changes significantly reduced field

failures.

EDUCATION

BACHELOR OF SCIENCE IN ELECTRONICS ENGINEERING TECHNOLOGY

DeVry Institute of Technology - Phoenix, Arizona

Summa Cum Laude - June 1990

Tau Alpha Pi National Honor Society

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