Summary

- Proficient in custom high speed analog/mixed-signal and RFIC layout

design, particularly at 90nm and 65nm processes technologies.

- Experienced in floor planning, placement and routing of macro

blocks, full chip integration and tape out.

- Experienced in physical verification including run file creation,

job running, strong debug and problem solving skill for LVS/DRC/ERC

and layout issues.

- Ability to work efficiently as a part of team as well as

independently with supervisory experience.

Specialties

- Knowledge of Cadence Virtuoso XL, Calibre, Hercules and DRACULA,

ASSURA, DIVA verification tools.

- Knowledge of UNIX and Linux systems, understand Perl and SKILL

language code.

- Highly motivated and able to learn and use new CAD tools,

processes, methodologies, creative and productive, able to manage

schedule to deliver projects on time.

- Strong analytical skills and communication skills with circuit

design background.

Professional Experiences

May 2010 - Current

Contractor, Mask Layout Design, Beceem Communications, Inc. Santa

Clara

Mask layout design for a RF chip, blocks and chip level, 65nm CMOS

process, Cadence VXL and Calibre.

April 2010 - August 2010

Contractor, Mask Layout Design, Infinera, Inc. Sunnyvale

Mask layout design for high speed (10-40Gb/s) photonic IC chips to

meet RC parasitic, IR drop and EM requirement from circuit design.

SiGe 65nm BiCMOS process, Cadence Virtuoso XL & Mentor Calibre.

September 2009 - January 2010

Contractor, RF & Mixed-Signal Mask Layout Design, Qualcomm Inc.,

Santa Clara

- Maintained full responsibility of mask layout design for new high

performance blocks used in a Wireless LAN product using 65nm CMOS

process using Cadence VXL.

- Chip integration and verification using Cadence and Mentor Calibre

CAD tools.

April 2007 - October 2009

Sr. Staff Analog Layout Design Engineer, Eastman Kodak Company,

Sunnyvale, CA

- Lead and maintained full responsibility of layout design for CMOS

image sensor chips including floor planning, layout creation for

IO's, bandgap, PLL, ADC, regulator, charge pump, etc. using Cadence-

Virtuoso XL and Mentor - Calibre, 0.13um, 0.11um,90nm and 65nm CMOS

process.

- Fully responsible for full chip integration, verification and final

tape out.

May 2004 - September 2006

Sr. Layout Design Engineer, OmniVision Technologies, Inc. Sunnyvale,

CA

- Responsible for CMOS image sensor chip layout design including

floor planning, layout creation using Cadence-Virtuoso, physical

verification using Cadence Assura and Mentor Graphics - Calibre,

0.13um, 0.11um, 90nm and 65nmCMOS process.

- Fully responsible for full chip integration and verification

(DRC/LVS/ERC) for final tape out.

June 2003 - May 2004

Sr. Layout Design Engineer, Lattice Semiconductors, San Jose, CA

Lead mask layout design for FPGA chip including floor planning,

layout creation for blocks and full chip integration and tape out

using Cadence-Virtuoso, physical verification (LVS/DRC) used

Cadence Assura and Mentor Graphics - Calibre, 0.13um CMOS process.

Sept 2001 - Nov 2002

Principal Layout Design Engineer, Spreadtrum Communications., Santa

Clara, CA

- Lead custom layout work of wireless communication chips using

Cadence's Virtuoso layout tool, 0.18um CMOS process. Custom layout

includes SRAM, I/O buffers, PLL,

D/A, A/D converters and other mixed-signal blocks. Responsibility

includes floor planning, key block layout and top-level

integration, DRC/LVS verification using Assura/DIVA, Dracula

and Hercules and deliver GDSII database.

- Responsible for full chip physical verification (DRC/LVS/ERC), RC

extraction and tape out database.

- Chip floor plan, P&R, clock tree synthesis, timing closure and ECO

using Avant!

July 1998 - Sept 2001

Sr. Staff Physical Design Engineer, Infineon Technologies Corp., San

Jose, CA

- Performed custom layout of standard cells, I/O buffers and SRAM's,

PLL, DAC for data-com, networking and DVD chips using Cadence's IC

layout tools, 0.25um and 0.18um CMOS process.

- Creation, debugging and maintain of LVS/DRC/ERC run files and

related script files. Run and debug LVS/DRC on IP libraries, module

blocks and full chip tape out.

- Floor planning, placement and route module blocks using

Apollo/Silicon Ensemble, including timing driven layout, clock tree

synthesis and ECO, metal fix revision.

- Bonding diagram layout using Infineon's in-house tool.

October 1994 - July 1998

Cirrus Logic, Inc. Fremont, California

Sr. Layout Design Engineer (12/1997 - 07/1998)

- Layout design for 8 bit DAC, PLL and VCO for graphics chips (135MHz

5V, 175MHz 3.3V, 250 MHz 3.3 V) using Cadence's IC layout tools.

- Created DRACULA LPE run file and ran layout extraction for back

annotation for high-speed mixed-signal circuit design.

- Floor planning, P&R of modules and full chip, running LVS/DRC/ERC

for all custom macros and full chip physical verification for final

tape out.

Analog Mixed-Signal IC Design Engineer (10/1994 - 12/1997)

- Responsible for circuit simulation, design modification and silicon

debugging of bandgap voltage reference circuit, which is used as on-

chip bias for D/A converter.

- Circuit simulation and design modification for 8-bit DAC, PLL and

VCO for graphics chips (135 MHz 5 V, 175 MHz 3.3 V) and LAGUNA-3D

chip (250 MHz, 3.3v).

September 1992 - October 1994

VLSI Design Engineer, Trident Microsystems, Mountain View, California

- Embedded SRAM circuit simulation and layout design for graphics

chips.

- Circuit simulation and layout design for CMOS standard cell library

and I/O buffers.

- Responsible for layout design of control logic and data path blocks

of graphics chip using symbolic layout technique with Cadence's

EDGE.

- Responsible for chip level floor planning, P&R, post-layout check

(DRACULA-LVS/DRC/LPE) and full chip tape out.

Education

MSEE, major in IC design, Clarkson University, Potsdam, New York

BSEE, major in semiconductor device and physics, Tsinghua University,

Beijing, P.R.China.

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