MOHANRAJ GOPAL

Phone : +91-890*******, +91-875*******

Email : abivkr@r.postjobfree.com

Address : **/*, *** ***** ******, Venkatappa colony, A.Narayapura, Bangalore, India.

Objective

Looking forward to work with a Company that provides me constant learning experience in the field of VLSI

Implementation.

Summary of Credential

Implementation of Perl based automation for mapping standard cell Libraries for DFT.

Comprehensive knowledge in Cellular Neural Networks (Wave Computing).

In-depth knowledge in MATLAB and Image Processing.

Knowledge in VLSI TESTING - SCAN and ATPG flow.

FPGA prototyping and verification – VHDL, Verilog & System Verilog

Work and Education

Internship in Tessolve Semiconductor Pvt. Ltd., Bangalore.

Master of Science in System on a Chip Program in Lund University, Sweden with GPA 4.08/5.

2 years as a Research Project Assistant in Waran Research Foundation, Chennai.

Bachelor of Engineering in Electronics and Communication, Anna University, Chennai with 74.3% (No

Backlogs).

Projects

CNN Design Flow Evaluation

Master Thesis in Lund University

DESCRIPTION :

Non-linear problems are found in day-to-day life which can’t be solved using linear algorithms. CNNs are massively

parallel algorithm which can solve computationally hard non-linear problems. CNN can be realized in hardware to solve

real-time problems like object recognition. There have been few realizatio ns done and the objective of this thesis is to

investigate the problems that will occur during a CNN hardware realization.

ROLES/RESPONSIBILITIES :

Creation of a MATLAB model for the CNN algorithm.

Use the MATLAB CNN simulator to analyze the criteria required for hardware realization.

Creation of RTL design for a Node Using VHDL.

Creation of generic parameterized network using VHDL.

Investigation of Pros and cons in a Serial Broadcasting Scheme.

Development of Instructions for simple image processing systems.

Idea for development of Vein feature recognition using CNN.

TOOLS : Xilinx ISE, MODELSIM, MATLAB

LANGUAGE : MATLAB, VHDL

SCRIPTING : TCL

PLATFORM : Windows 7

Optimal solution for CNN Boundary Nodes

As a Research Assistant in Lund University

DESCRIPTION :

This Project is a continuation of Master thesis. The functional correctness of Cellular Neural Networks depends on the

design of its boundary nodes. The objective is to investigate the three boundary conditions and its effect on various

scheduling techniques.

Investigation of three Boundary Conditions Fixed, Periodic and Zero-flux.

Implementation of the Boundary Conditions.

Observation of Area and timing dependencies.

Recording the results made during the observation.

TOOLS : CNN Simulator, Xilinx ISE, MODELSIM

LANGUAGE : MATLAB, VHDL

PLATFORM : Windows 7

Multiple clock GALS Design using Caltrop Actor Language (CAL)

Self-Project in Lund University

DESCRIPTION :

AES is very commonly used Encryption algorithm. AES implemented in a hardware can be cracked using Differential

Power Analysis (DPA). ETH Zurich implemented a GALS based AES cryptographic accelerator to resist Differential

Power Analysis attacks. The Objective is to mimic the Zurich Implementation in CAL.

ROLES/RESPONSIBILITIES :

Thorough Investigation of the ETH Zurich’s GALS system.

Implementation of GALS system for AES in CAL.

Conversion of CAL source to VHDL.

Area and timing comparison with respect to Zurich’s GALS system.

TOOLS : Open RVC-CAL compiler, CAL-RTL Convertor

LANGUAGE : CAL, VHDL, Perl

SCRIPTING : Shell

PLATFORM : Linux (Cent OS)

Speaker Recognition using MFCC

Course Project in Lund University

DESCRIPTION :

MFCCs (Mel Frequency Cepstral Coefficients) which model the variation of human ear’s critical bandwidths were used

to extract the feature set from a speech signal, which in turn were used for pattern recognition.

ROLES/RESPONSIBILITIES :

Implementation of Recognition algorithm in TMS320C6713 DSK Board using C (Code composed Studio).

Creation of Templates by extracting MFCC Coefficients.

72% Success rate in verification of different Speakers.

TOOLS : Code composed Studio

LANGUAGE :C

PLATFORM : Windows 7

Kaeru Jump Game using Nexus 2 FPGA Board

Course Project in Lund University

DESCRIPTION :

Replica of the famous internet flash game ‘Kaeru Jump’ is created in embedded platform using Nexys2 FPGA Board.

ROLES/RESPONSIBILITIES :

The game logic was implemented using embedded C in Microblaze soft processor.

The VGA and PS2 drivers are implemented in Hardware.

Integration between hardware and software is done using Shared memory architecture

TOOLS : Xilinx ISE & EDK

LANGUAGE : VHDL, embedded C

PLATFORM : Linux (Cent OS)

Hardware based Image Viewer and Encoder - ASIC Design

Advanced Course Project in Lund University

DESCRIPTION :

JPEG Compression with Huffman encoder and decoder was implemented in hardware using 130nm technology. The

implementation was verified using virtex II pro FPGA Board.

ROLES/RESPONSIBILITIES :

RTL Design of Jpeg Compression with Huffman Encoding.

Better throughput achieved by using Aggoun and Jalloh proposed transpose buffer.

Synthesis using Design Vision and optimization of Critical path.

Post-synthesis Simulation with the generated netlist.

Place and Route using SOC encounter.

Post-layout simulation and identify the Glitches and violations.

Also verified the RTL design in virtex II pro FPGA.

TOOLS : MATLAB, Modelsim, Design Vision, SOC Encounter

LANGUAGE : VHDL, MATLAB

PLATFORM : Linux (Cent OS)

Simulating MIP cells and ALFUs of MIP SCOC in Verilog

As Project assistant in Waran Reasearch Foundation

DESCRIPTION :

MIP SCOC is a future supercomputer design paradigm developed at WARFT. Read more on MIP -SCOC here.

ROLES/RESPONSIBILITIES :

Implementation of Six MIP cells using Verilog.

Implementation of ALFUs (Carry Save Adder, Multiplier, Matrix Addition, Matrix Multiplication, Comparator)

using the MIP cells.

TOOLS : ModelSim

LANGUAGE : Verilog

PLATFORM : Linux (Cent OS)

Face Recognition Using WMPCA

Bachelor Project in Jeppiaar Engineering College (Anna University).

DESCRIPTION :

WMPCA is the extension of the PCA face recognition algorithm that exploits parallelism in hardware. A software model

of a real time Face recognition algorithm using WMPCA in MATLAB.

ROLES/RESPONSIBILITIES :

Implementation of face extraction algorithm from group photos.

Implementation of WMPCA face recognition algorithm.

TOOLS : MATLAB

LANGUAGE : MATLAB

PLATFORM : Windows XP

Skill set

VHDL, Verilog, System Verilog ModelSim & QuestaSim

C, C++ Mentor Tessent

Perl, TCL and Shell Xilinx ISE & EDK

MATLAB Synopsys Design Vision

CAL Cadence SOC Encounter

Assembly level Programming TI Code Composer Studio

Cadence ICFB & Virtuoso

Other Activities and Hobbies

Listening to Music, Playing Cricket and basketball

Gaming – First person shooting, strategy

Testing Android ROMs.

Contact this candidate