Manager Engineer
Resume:
Mike Rodgers
Mountain View, CA **040
abili3@r.postjobfree.com
http://www.linkedin.com/pub/mike-rodgers/4/a27/7a6
Career Summary
. Extensive experience and outstanding achievements in various technical
and management roles in Q&R, CAD, VLSI chip fab, assembly, & test
factories and CPU product development, testing, debug, failure
analysis, and DF* for Intel CPUs.
. Strong proven record in consistently managing and solving the most
complex technology and business challenges from Q&R to CAD, design and
test.
. In depth expertise in device physics, product development, product and
process Q&R methods, failure analysis techniques, CPU and memory
testing, defect screening methods / effectiveness / prediction, chip
manufacturing processes, team building, and leadership.
. Key results include more than $3B in test capital savings while
modernizing both on-chip DF* schemes as well as new scalable test
methods and equipment paradigms that delivered world class quality
product. Defined, lead and drove ATE/test industry paradigm shifts
such as DFT ATE, Open Arch ATE, and Adaptive Testing.
. Extensive experience in staffing and managing large cross discipline,
cross business group technical teams, driving industry paradigm
shifts, leading test technology planning and integration, solving
customer technical problems, driving industry DF* and industry wide
test benchmarking (internal and consortia), & developing predictive
Q&R tools.
. Built and managed the world's 2nd largest chip design technical
conference while establishing new innovative online and interactive
access technologies at a world class lowest cost per attendee.
. Author and invited featured speaker, numerous technical papers,
publications, & conferences.
Professional Experience: Intel Corp, Santa Clara, CA (1986-2006)
Manager, Co-Chair, CPU/chipset Test Technology Planning & Integration (1997-
2006) Managed high level Cross discipline / cross business unit DFT/Mfg
Test Process technologies, metrics, roadmaps. Achieved > $3B of capital
savings via focusing on fleet re-use, new equipment paradigms, innovative
test methods, expanded and more capable DFT, used on reduced pin count,
lower cost ATE in high volume manufacturing.
Drove new structural testing: DFT, test methods, and test mfg process
paradigm shift across the corporation that reversed increasing test cost /
DUT trends while delivering world class product quality and reliability.
Manager, Cache Test Technology (1993-2006) Lead & managed corporate
interdisciplinary teams that established world class Cache Design, DFT, and
Test methods. Lead CAD development that produced unique DFT and test
generation and validation tools which reduced test generation efforts by an
order of magnitude across Intel CPUs. Developed DFT and test methods that
reduced development NRE and production test times for embedded caches by
10X while delivering defect free arrays across generations of Intel CPUs.
These still far exceed methods in use by most other semiconductor providers
today. Drove in-field self repair for large caches. Administered academic
research in defect fault types & screening methods for multi-ported arrays,
linked faults, SRAM delay faults, and overall test pattern fault models and
coverage.
Manager, Design and Test Technology Conference (2000-2006) Chaired and
managed annual internal world class design technical conference (Design,
Test, Validation, Debug, & Platform disciplines). Delivered lowest cost
(by >50%) / attendee events '00-'06 while dramatically increasing use of
the web and streaming video to expand online audience (1000x increase in
technical content distribution), increased technical content quality &
competitiveness, expanded technical content focus areas and live event
networking. Grew to >900 submissions, currently 2nd largest design tech
conference worldwide. Overhauled and redesigned organization
infrastructure, processes & efficiency: managed over 1000 support personnel
in a dozen virtual departments to deliver 50% more technical content & live
event at greatly reduced effort. Drove software development for managing
all aspects of technical content evaluation, management, and development
processes. Supervised executive talks' selection and content development,
from internal and external Sr. VPs, CEO, and technical Fellows.
Negotiated with host facilities and subcontractors, establishing long term
relationships with convention centers, and established industry leading
cost saving precedents, and re-use through hotel/facility/sub-con
contracts.
Co-Chair, International Technology Roadmap for Semiconductors Test
TWG/Chapter (1999-2006) Lead cross industry expert team to deliver annual
roadmaps to drive equipment and EDA vendor base capabilities for future
technologies (up to 15 year horizon). Expanded membership to include
academic and vendor participants, greatly increasing influence of the
roadmap identified test challenges on academic and consortia (GSRC, SRC)
research focus and investments. Currently, this effort is increasing work
across the industry on test enabled yield improvement methods, reliability
screening and defect and at end used error correction.
Co-founder and Intel representative, Sematech Test Council (1999-2006)
Founding and ongoing participant in test industry benchmarking team
comprised of Sematech members. Designed annual test metrics survey to
collect and distribute metrics and distributions anonymously among members.
Designed, hosted, participated in annual mfg test plant tours across
participating member factories. Drove key industry focused discussions and
evaluations on strip testing, RF testers, ATE platform cross company user
groups, test power technical challenges and mfg practice, and Gb/s I/O DFT
and Test Methods. Drove "DFT Tester" thrust that resulted in ITRS
definition in '99 and ATE industry platform paradigm shift demonstrated by
"DFT ATEs" available from all major vendors by '02
Formed and managed Test Technology Q&R (1995-1997) Developed quantitative
compound coverage metric based product test quality DPM indicator and tools
that took into account logic fault coverage (stuck-at and speed test
coverage) and memory test heuristics models to accurately predict outgoing
DPM across several generations of CPUs. This tooling is an essential part
of the DFT definition process across Intel products in development
worldwide today. Set corporate requirements for fault grading on logic
products and embedded memory DFT / testing. Established change control
systems for test program revisions that reduced program errors by an order
of magnitude. Established target specifications and certification
processes for scan and other new CPU DFT technologies. Drove development
of experts' body authored & juried extensive Intel Test Methodology
Handbook (~1000pp) which continues to be used as detailed technical
training manual for PEs and Q&R engineers and to set requirements for
testing across products today. Staffed scan diagnostics tool experts team
that developed and delivered world class scan diagnostics tooling that far
exceeds commercial tooling in terms of efficacy on partial scan designs,
fault isolation accuracy, and integration to factory low yield analysis
processes. Use of this tooling provided breakthrough analysis results
resulting great reduction in product/process issue debug (months/product)
and substantial yield upside (yield increases in dozens of die/wafer on
130, 90, and 65nm technology CPUs and chipsets).
Managed Mobile Group Product Q&R (1991-1994) Managed Product Q&R for mobile
group CPUs and chipsets on dedicated mobile Pentium and SL based product
lines, including development and execution of qualification plans,
management of product debug and failure analysis, and response, containment
for various customer issues from Pentium floating point errata to systemic
process defects. As Q&R Liason to Boca Raton IBM/Intel joint venture for
future CPUs delivered FA technology training and coordinated overall
project DF* (test, reliability, debug) planning.
Managed A/T Factory Q&R group (1995) Co-developed extensive overhaul of
CPU Test Program Release processes that addressed systemic and random test
program related test escapes, program flow errors, and greatly reduced
customer exposure. These code checking, heuristic, and data collection
verification processes continue to run across Intel test factories today.
Drove successful overhaul of factory processes to reduce administrative
quality DPM escapes rates by an order of magnitude, including extensive
automation and factory WIP flow process improvement.
ERT Building Coordinator (1990-1995) Staffed, trained, and lead new ERT
team for renovated medium risk combined office space / test factory /
laboratory facility. Designed and implemented multi-tiered multi-aspect
incident command structure, reinforced through regular complex drills and
coordination with site and corporate safety, incident command, risk
management, and local public safety officials.
Managed Component Failure Analysis teams (1990-1991) '91-Managed Santa
Clara based Failure Analysis engineering team, primarily responsible for
analysis of product qualification fails, customer returns, and support of
new product debug. Coordination with FA Technologies group in development
and deployment of new fault isolation and failure analysis techniques. '90-
Managed Japan based customer Q&R service center and FA engineering team.
Coordinated and delivered technical customer reports on major reliability
excursions in numerous on site visits. Developed fail signature based
system for recognizing system failure patterns across populations of
customer returns and other fail unit sources. Established priority
classification for failure analysis processing to greatly increase value of
FA results with respect to customer's prioritized needs.
CPU Product Line Q&R Manager/Engineer (1986-1990) Supported and executed
DF*, all product debug and qualification, and needed product failure
analysis of CMOS 286 and i860 CPU families, responsible for and reporting
to business group manager on all Q&R aspects of product lines for 286 and
i860 families. Called in to debug and analyze complex bipolar logic chip
system field failures to root cause and to develop and deliver technical
summaries of detailed product FA results and systemic metallization
improvements to worldwide customer base. Did similar for other product
lines and debug of major process/product interactions, up to and including
delivering complex technical messages on analyses, containment, and
solutions to the customer base in person and through worldwide field
support. Co-developed major overhaul of corporate product qualification
methodologies and definitions.
Pre-Intel Employment:
University of Illinois-Chicago Microelectronics Lab, Process Engineer and
Technical Support (1984-1986) Sole process engineering support for
graduate students' and Microelectronics Lab Director's innovative device
design and fabrication projects, including maintenance and rebuilding of
antiquated semiconductor fabrication equipment and laboratories.
Discreet Bipolar Fab Product/Process/Design Co-op Engineer, National
Semiconductor, Danbury, CT (1983-1986) Co-op product engineer on diverse
discreet bipolar and JFET product lines varying from RF transistors to gold
doped bipolar transistors to mesa power transistors and darlington amps.
Range of activities to improve yields included regular analysis of lot test
chips with respect to theoretical device physics of fab and electrical
parameters and historical heuristics to achieve desired operating
specifications and yields. Device re-design and process recipe
manipulation based on device physics, empirical metrics results, and
industry established heuristics were all used regularly to redesign
products and processes to consistently get 10,000 different product
specifications at high yields out of a fab line running 100 different
processes on 20 year old equipment.
Education / Professional Associations
BSEE University of Illinois Chicago, minor in Computer Science
University of Chicago, in depth studies in Physics, French, Far Eastern
Languages and Civilizations
Languages: Excellent English skills; limited written and spoken fluencies
in Japanese, Spanish, French
Professional Photographer, Videographer, & Chef
Publications
Author, co-author on numerous papers on Test Process
Integration/Partitioning, Embedded RAM testing, Technology Roadmaps, and
Future Test Challenges
Co-Author / Presenter (with IEEE fellow Yervant Zorian) IEEE Workshop Test
Resource Partitioning
Primary Co-author, VTS'01 Keynote from Intel VP Jai Hakku introducing "Open
Architecture ATE"
Primary Co-author, ITC'97 Keynote from Intel Sr. VP Pat Gelsinger "Testing
Billions of Devices in the Internet Era" that lead to ATE definition / DFT
usage paradigm shift in semiconductor testing and ATE business
References
More detailed recommendations from CEOs, Fellows, and Senior Technical
Staff at http://www.linkedin.com/pub/mike-rodgers/4/a27/7a6
Chris Hampson, Intel, Sr. Principal Engineer, Manager X86 Cache Test
Development PE team, Chair, Intel Cache DFT/Test JET (X-discipline/biz
group joint engineering)
David Wu, Intel, Sr. Principal Engineer, Manager Q&R DF* Team
Greg Spirakis, Intel (ret.), MG VP and GM Design Technology (corporate CAD
group)
Wayne Needham, Intel (ret.), IEEE Senior Member, World's 1st CPU Product
Engineer (on 4004 CPU) and overall semiconductor industry Test Expert
Babak Sabi, Intel, TMG VP and GM Corporate Quality Network
Dr. Valluri (Bob) Rao, Intel, fellow, former Director of FA Technologies,
currently MEMS and Silicon Systems technical lead
Dr. Paolo Gargini, Intel, fellow, Director, Technology Strategy, Technology
and Mfg Group (TMG)
Dr. Paul Ryan, Intel, Co-Manager Product Development Technologies Q&R
Dr. Mike Mayberry, Intel, TMG VP and GM, Components Research
Dr. Phil Nigh, IBM, Test Methods / Defect Screening Strategist
Dr. Yervant Zorian, VP Virage Logic (EDA), IEEE Fellow
Dr. Ad van deGoor, Delft University (ret.), IEEE Fellow and world renown
memory test expert
Dr. Edward J. McCluskey, Stanford University, Director, Center for Reliable
Computing, IEEE, ACM, and AAAS Fellow
Nancy Johnson, US Congresswoman (ret.), Connecticut 5th District (1980-
2006)
Contact this candidate