Engineer Software
Resume:
JEFFREY A. ACREE
Hillsboro, OR. 97124
abiflc@r.postjobfree.com
EDUCATION: Bachelor of Science Electrical Engineering, 1986
University of Maryland, College Park, MD
EXPERIENCE:
EVE_USA, San Jose, CA. February 2008 -
June 2010
Sr. Applications Engineer
- Emulation model development and verification for EVE models and
simulation
- Cycle based simulation model development
- RTL synthesis to gate level EDIF netlist targeted for Xilinx FPGA
- Place and route Xilinx FPGA flow.
- Using System Verilog, verilog and VHDL RTL languages
- Detailed knowledge of System Verilog, verilog -2001, verilog and VHDL
- Scripting including Perl, Awk and Sed
- Debugging embedded hardware and software
- C++ testbenches to drive emulation
Novas Software, San Jose, CA. - October 2002 - January
2008
Sr. Applications Engineer
- Software demos and presentations of Novas software feature set ie
Debussy, nLint, Verdi
- Software training to new and existing customers.
- Detailed knowledge of System Verilog, verilog -2001, verilog and VHDL
- Working knowledge of PSL, OVA, System C, Vera, specman e and
transactions
- Detailed knowledge of SOC ASIC flow from System level, RTL, gate to
layout
- Wrote several TCL applications for new software tools to be sold
- Territory included Pacific Northwest, Southwest region and Israel
- Working as tools and system verilog consultant on next generation
microprocessor at large company
- ERC and DRC checking on large designs for semiconductor company.
- Primetime timing analysis checking
LSTG Synopsys, Beaverton, Oregon - January 2000 -
October 2002
Corporate Applications Engineer
- Responsible for test, presentation, training and customer rollout of
embedded 68HC11 and 8051 processor cores for ASIC design flows.
- Familiar with 68HC11 and 8051 assembly language code.
- Responsible for developing and demonstrating synthesizing DesignWare IP
products at trade shows.
- Responsible for FAE/customer demos, presentations and training in
Hardware Model, FlexModels, Mempro, VMC/CMC/VHMC simulation modeling
technologies.
- Very familiar with Synopsys ASIC synthesis Design Compiler tool.
- Demonstrate EAGLEi HW/SW coverification products at embedded system
trade shows.
- Advanced C++ graduate class training, System C training, basic and
advanced synthesis training, WindRiver embedded OS core training.
- Develop product demos for VMC/CMC/VHMC.
Synopsys, Beaverton, Oregon - January 1998 -
December 1999
R&D Software Engineer. LSTG
- Software development engineer using C in a UNIX and NT environment.
- Responsible for developing interface between FlexModel technology and
supported digital VHDL/Verilog simulators.
- Extensive knowledge of MTI Modelsim VHDL/Verilog, Cadence Verilog -
NC/XL, Veribest Verilog/VHDL, Synopsys Scirocco, Cyclone and VSS
simulation products.
- In depth knowledge of VHDL/Verilog.
- Extensive knowledge of Make, PERL and UNIX scripts to run and verify
software builds and release tests.
- Familiar with JAVA and C++.
- Familiar with software debuggers such a gdb, dbx and ddd.
- Familiar with IP based tools such as VMC/VHMC and CMC.
- Familiar with Vera testbench language.
- Some experience with supporting PCI/PCI-X bus architecture and bus
protocols.
- Developed production software using Atria build and release environment.
- Performance testing using "Quantify" and memory checks using "Purify".
- Added enhancements to Swift Library code for Teredyne Lasar simulator.
- Responsible for Mentor Graphic's "Swift Interface" and Hardware Model
"Model Access" code.
Mentor Graphics, Wilsonville, Oregon - March 1996
- January 1998
Technical Marketing Engineer
- Technical marketing on QuickHDL Pro, QuickSim II, SimView simulation and
VHDLwrite
- VHDL netlist generation products.
- Developed customer presentations and demos on QuickHDL Pro, QuickSim II
and
- QuickHDL products.
- Wrote and debugged Verilog and VHDL designs using QuickHDL and Modelsim
products.
- Field AE and customer training on QuickHDL Pro and QuickSim II products.
- Field marketing and customer support on technical aspects of all
products supported.
- Performance testing and benchmarking.
- Customer requirements gathering for enhancements to QuickSim II and
QuickHDL Pro.
- Project engineering manager on VHDLwrite product.
- Customer trade shows at MUG 96 and 97, DAC 96 and IVC/VIUF 96 and 97.
- QuickHDL Pro demos in demo suite at DAC 96.
- Have had TCL training and have some current working knowledge of TCL
language.
- Have taken advanced VHDL, Verilog and PLI training courses.
Graphics, Wilsonville, Oregon - January
1993 - March 1996
Customer Support Eng. Mentor
- Customer support involving QuickHDL, QuickSim II, System1076, Continuum
and
- QuickHDL Pro simulation products.
- Wrote Verilog and VHDL to reproduce problems and verify functionality in
QuickHDL.
- Customer support project team member on FlexSim simulation project.
- Customer support involving Mentor's AMP/technology file and BLM library
models.
- Develop and/or debug customer test cases to reproduce software defects
and develop
- timely work around for the customer.
- Generated detailed defect and enhancement reports to engineering.
- System Administrator and ASIC librarian for Digital simulation customer
support team.
- Develop knowledge based solution records and customer support bulletins.
- Consistently had the top percentage of calls taken and best resolution
time over one year
- period.
- Thorough knowledge of AMPLE userware simulation language.
- Completed development of 900 part AMP library for NAVAIR library
contract working as a
- contractor for Performance Computing Inc.
Multilogic, Hillsboro, Oregon - 1992 -
January 1993
Software Modeling and Q/A Engineer
- Wrote behavior modeling Verilog/C code to create Verilog based
simulation models.
- Tested, debugged and verified functionality of Verilog/C models using
Cadence Verilog XL.
- Quality Assurance Engineer for VHDL PLD/PAL compiler and synthesis tool.
- Main duties included regression testing, analyzing and debugging VHDL
compiler and synthesis software on a weekly basis for engineering team.
- Wrote new VHDL tests (RTL and gate level) in order to test new features
of VHDL compiler
- and synthesis tool.
- Modified existing VHDL tests in test suite to verify current
functionality.
- Simulated and verified results of test suite using Cypress
Semiconductor's Simulation Toolkit.
- Wrote DOS scripts, automated and maintained VHDL test suite in a PC
environment.
CAE Link Flight, Sunnyvale, CA - 1989 -
1992
Hardware Design Engineer
- Design, simulation, layout and testing a 350 IC digital circuit board
consisting of FAST
- and CMOS logic families used in RADAR simulation.
- Circuit board consisted of 32x32 MAC's, 16 bit ALU's FIFO's, RAM's, data
PROM's, state
- machines, PLD's and PAL's.
- Designed, simulated and packaged board using VALID/Scald work stations
- PLD's and PAL's designed using ABEL and CUPL software.
- State machine and PROM firmware developed using C and FORTRAN.
- Tested board by generating C driven test vectors and UNIX shell
utilities.
- Hands on experience using oscilloscope, logic and spectrum analyzers.
- Completed design project ahead of schedule and was responsible for 6
RADAR boards during
- hardware/software integration.
- Led design reviews on circuit card progress schedule.
- Card emulation routines written in FORTRAN.
CAE Link Tactical Div., Silver Spring MD - 1986 - 1989
Hardware Design Engineer
- Design, simulation, layout and testing 5 digital and 1 analog board used
in SONAR simulation.
- Digital designs included a 4x128 - 64 point FIR filter board, 8M x 8 bit
DRAM memory board,
- sum node and SONAR type algorithmic boards.
- Analog design included a low frequency FM modulator with a AM modulated
phase.
- Analog design contained 16x4, 16, 12 and 8 bit DAC's, op amp functions
and drivers,
- oscillators, band and low pass filters, multipliers, rectifiers,
triggers, regulators, caps and
- resistors.
- Designed, simulated, timing verified and packaged boards using
VALID/Scald work stations.
- PLD's and PAL's designed using PALASM.
CLEARANCES: DOD Secret with special access.
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