Design Project
Resume:
V N Pradeep Kumar Kaja
**** * ******** **, *******, IL-60612. 1-
*******.****@*******.***
Summary
. Design and Development experience in using cadence (schematic, virtuoso,
spectre and diva) tools.
. Strong knowledge in Testing of VLSI circuits using Atalanta and also
Test data compression techniques.
. Significant knowledge in design of Op-Amp based current mirror,
amplifiers and filter circuits through H-SPICE.
. Adequate knowledge in characteristics of MOSFET and CMOSFET based digital
circuits.
. Excellent communication, leadership and interpersonal skills, a team
player with good analytical skills.
Education
Master of Science University of Illinois at Chicago (Jan 08
- May 10)
Major: Computer Engineering Current GPA: 3.76/4.0
Bachelor of Engineering Sathyabama University
(Aug 03 - May 07)
Major: Electronics & Communication Engineering GPA:
3.85/4.0 (86.67%).
Skills
Programming Languages : VHDL, Verilog, Perl Scripting, MATLab, C, C++
and Java.
Design Automation Tools : Cadence (Schematic, Virtuoso, Spectre and diva),
Altera Quartus II, VPR with T-VPack, Xilinx ISE 11, ALDEC
Active HDL 7.2.
Others : H-SPICE, Synopsys Scirocco
Simulator and DC, ATPG-Atalanta, P-SPICE, Cygwin, PCSPIM.
Experience
Research Assistant in ECE Department University of Illinois at Chicago
(June 2010)
. Currently working on a group project for development of a c6
(Computation, Cooperation and Competition on Common Resources in a Large
Community under Limited Connectivity) toolset for Nano-Electronic based
system.
. This tool takes user defined plugins as inputs to reconfigure the
interconnect network topology to make the system fault resistant.
Other Roles
. As a Graduate Assistant maintained database and website for MSCS
Department of UIC. (Aug 08 - May 10)
. As a Program Analyst Trainee for Cognizant Technology Solutions (CTS)
learnt SQL, Informatica. (Aug 07 - Nov 07)
Projects
4-Bit Universal Shift Register (Cadence Virtuoso, TSMC
65nm CMOS)
. Developed a layout for 4-Bit Universal Shift Register from basic P-MOS
and N-MOS layouts using Virtuoso Cadence tool and its LVS is matched.
. Acted as Team Lead, assisted Team mates in project planning, Design and
debugging.
. It was recognized as the best project in terms of the area and delay,
where we calculated area as 4492203 sqlambda and delay as tphl = 0.27ns and
tplh = 0.13ns.
. Played key role in finding issues when routing with same and different
sublevels of metal layers.
. Assisted other team mates in using shot finder of Cadence tools.
Test Compression and Compaction (Atalanta-M 2.0, MATLab,
VHDL, XILINX ISE)
. Compressed, Compacted and Decompressed test data, for ISCAS 89 sequential
circuits, obtained from Atlanta ATPG.
. The Fully Specified test vectors for ISCAS 89 sequential circuits are
ordered and encoded in EFDR using MATLAB.
. Primary contributor implementing new techniques for encoding in MATLab
when compression is not achieved through implemented techniques.
. Responsible for implementing De-compressor, RLE encoding technique, in
VHDL, testing it using Active HDL and synthesizing using XILINX ISE
Webpack.
Retiming Synchronous Circuit (Java, VPR & T-VPack)
. Developed a Simulator which takes a synchronous circuit in .blif format
and gives retimed synchronous circuit in the same .blif file format using
Java.
. Implemented entire simulator using the simple Traveling Salesman
Algorithm.
. The output file obtained from the simulator is placed and routed using
VPR & T-VPack.
. Simulator with restriction on number of registers that can be added has
achieved a decrement in critical delay from 21esec to 13esec.
. Simulator with no restriction on number of registers has achieved a
critical delay of 9esec.
H-SPICE based Simulation Projects (H-SPICE)
. Designed and implemented many Op-Amp based circuits such as Low and High
pass filters, voltage followers and integrators etc using H-SPICE.
. Implemented MOSFET based current mirror and amplifier circuits using H-
SPICE.
. The characteristics of such circuits are learnt by simulating the
circuits in H-SPICE and analyzing the results.
VHDL based Projects (VHDL, Synopsis Scirocco Design
Compiler, Xilinx ISE)
. The below stated projects are coded using VHDL simulated using Synopsys
Scirocco simulator synthesized either by Synopsys Scirocco Design Compiler
or by Xilinx ISE Webpack 11.
. CPU, CMI and Memory Unit
. Two Input Finite State Machine
. RC6 - Encryption
. 32-bit Booth Multiplier and Add & Shift Multiplier Simulation
. 16-Bit Comparator
ATPG & Fault Simulation Functionalities (Atalanta-M 2.0)
. Generated Test Vectors for ISCAS85 benchmark circuits using Atalanta.
. Simulated the circuits with same number of random generated vectors and
compared with fault coverage of ATPG test vectors.
. Increased the number of randomly generated test vectors and understood
the variations in fault coverage.
. Compared the run times for ATPG generated and randomly generated test
vectors.
Automatic Railway Signaling
. Developed a new sensor, a combination of thermistor and spring, to sense
the rail friction and weight of train.
. This reduces the cost by 5 times, instead of using the traditional IR
sensor to detect the train.
Papers & Course Work
Literary Survey on DFY
. Learnt how to analyze yield using the Poisson's and compound poisson
distributions for chip consisting of two different types modules with
redundancy and chip kill circuitry, this can also be applied to more number
of modules.
. Understood how the introduction of redundancy in memory and logic
circuits affects the yield.
. Studied the techniques such as layout and floor-plan modification for
improvement of yield in logical circuits.
Other Papers
. Written a paper as required for the course work on efficient conversion
of Solar to electrical energy using SWNT.
. Gained knowledge on H-SPICE by doing different experiments on OP-Amp's.
CCNA Certifications
Network Fundamentals Routing Protocols LAN Switching and
Wireless Accessing WAN
Relevant Courses
Testing & Reliability for Digital Systems Physical Design
Automation
Advanced VLSI Analog VLSI
Introduction to VLSI Digital System Design
Advanced Computer Architecture Computer System Design
Nano Electronics CAD Based Logic Design
Achievements
. Won the Inter College Chess Title twice.
. Played as hockey goal keeper in Inter College championship.
Contact this candidate