Engineer Design

650-***-**** mailto:**********@***.***

Mountain View, CA 94043

Ed Spence

Objective Senior Mask Designer/Layout Designer

Qualifications Over 15 yrs. experience in Analog/Mixed Signal

layout design

Skills include Cadence Virtuoso XL, Diva, Assura,

Hercules, Dracula verification, VAVO/VAEO, Analog

Artist Composer, Spectre, UltraSim, Aptivia,

Unix/Linux, MS Excel, Word, Powerpoint, C-shell,

Perl, Awk, sed, C, Emacs editor, HTML, Windows.

Basic understanding of semiconductor devices as

well as CMOS and bipolar processes. Demonstrated

proficiency in block level floorplanning,

understanding of design rules, minimization of

parasitics, isolation techniques, device matching,

etc.. Designed and laid out 3 full qual vehicle

test chips from start to finish.

Excellent team player with multiple bonus awards

for exceeding expectations, such as 'attention to

detail' in finding design flaws in various IC

designs before tapeout of ASIC gate array designs,

Telecom group designs, and new process Qual

Evaluation Vehicles. Part of long-standing Key

Employee Incentive Program.

Experience 1/2006 to 3/2009 National Semiconductor

Corporation

Principal CAD Engineer/Qualification Evaluation

Vehicle group/ Advanced Process Technology Division

Responsible for design, schematic capture,

simulation, layout, verification, tapeout,

test/characterization documentation of new fab

process qualification test chips and technology

benchmarking circuits, which resulted in receiving

an achievement award and recognition for

"successful designs, accuracy, timely delivery,

meeting customer commitments and contributing to

National's growth."

Designed and laid out Optimos2 new process qual

vehicle test chip from start to finish, resulting

in a record first-time success of a qual vehicle

test chip, and published document on "First time

success factors" on the group website.

1997 to 2005 National Semiconductor Corporation

Principal Product Engineer/Custom Solutions Group /

Emerging Products Division

Provided layout database Design Rule Check

(DRC)/merge/fracture service prior to mask making

for each customer-designed device

Supported external customer design centers with

National's latest tools and libraries for

National's leading-edge technologies including

CMOS7, CMOS9T, ABCD150, BiCMOS7.

Created and maintained a Private Account Portal

website for each external ASIC customer design

center to access the necessary tools and libraries,

and provided customer design support, resulting in

a bonus award for customer satisfaction.

Examples of the latest customer-designed devices

and support include:

MICROSOFT FM radio receiver chip which included

entire analog frontend including AGC, IF,

demodulator, and embedded RAM - full chip schematic

capture (200 pages) and Hercules DRC/LVS and layout

for redistribution metal, which resulted in bonus

of 5 Microsoft software titles for customer

satisfaction.

1996-1997 National Semiconductor Corporation

Principal Product Engineer/Telecom Product

group/WAN Division

Design support for Telecom designs including:

Full chip LVS using Dracula, which resulted in a

bonus award and recognition for "long hours and

attention to detail in completing the 2B1Q NT1"

chip, when a layout design flaw was found and

corrected before tapeout.

1985-1996 National Semiconductor Corporation

Principal Product Engineer/High Performance ASIC

group/Gate Array Division

Gate Array customer design reviews, database prep.,

including one AT&T design place & route rework done

at Boston Design Center, which resulted in

first-time silicon success and achieving the

highest yielding product of all.

Developed NGP1000 2.5GHz PLL gate array test chip

layout; spectre simulation; lab characterized 12

versions

BiCMOS/ECL Gate Array NGX core library design,

layout & silicon characterization (MB8851 test chip

full design & layout), which resulted in the new

technology gate array meeting the market window.

Cray Research BiCMOS/ECL test chip full design,

layout & characterization

Failure analysis

Education

BSEE with a minor in computer science from Cal Poly

State University, San Luis Obispo, CA

Cadence Analog Artist and Mixed Signal training

Various technical classes offered at National

Semiconductor University including Fundamentals of

Mixed Signal Testing by SoftTest and New Analog

Structured Design by Prof. Middlebrook, Cal. Tech.

C-shell, C programming, Perl, Emacs editor

Keywords(ASIC, development, DRC, LVS, layout,

Cadence Analog Artist, Virtuoso Composer, VXL,

Assura, RCX parasitic extraction, Hercules,

StarRCXT parasitic extraction, Spectre, UltraSim,

characterization, verification, failure analysis,

Unix/Linux, MS Excel, HTML)

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