Engineer Design
Resume:
KERIN T. WALSH
Swampscott, MA
*******@*******.***
PROFILE Experienced engineer skilled in solving applications support
issues in both hardware and software environments. Detail-driven
with outstanding communication skills and proven success
interfacing with both customers and co-workers.
EXPERIENCE Senior Staff Design Engineer (February 2003 - October 2009)
Senior EDA Engineer (May 1996 - February 2003)
Toshiba America Electronic Components, Inc., Marlboro, MA
. Implemented, modeled and verified RTL Verilog and Synopsys
liberty models for IP offerings.
. Developed test plans and verilog testbenches for IP
offerings and performed SOC verification using Verilog
simulation tools.
. Defined and implemented procedures to ensure timely and
accurate model release to customers. Documented and tracked
releases.
. Served as liaison between design, engineering and customer.
. Developed data sheets and authored white papers on front
end modeling techniques.
. Provided worldwide support to Toshiba design engineers and
customers for simulation and verification issues.
. Evaluated and benchmarked front-end simulation,
verification and timing analysis tools.
. Developed and taught customer training classes for Toshiba
ASIC Sign-off flows.
Senior Applications Engineer (September 1993 - May 1996)
i-Logix, Inc., Andover, MA
. Provided first-line technical support to domestic
customers, AEs, and international distributors for Express-
VHDL and Statemate products.
. Supported complex and mission critical products used in
aerospace, automotive and other embedded systems
applications.
. Worked with sales and marketing organizations to ensure
technical success with prospective clients.
. Defined and drove QA strategy for product testing. Acted as
liaison to development in communicating product defects.
. Developed and taught product training classes.
Senior Engineer (January 1989 - August 1993)
Raytheon Corporation, Marlboro, MA
. Implemented and synthesized 30K gate cache controller ASIC
in VHDL. ASIC interfaced cache memory, PI bus and MIPS
R3000 based microprocessor.
. Designed state machine for 50K gate address generator ASIC
using Mentor's design tools.
. Designed, programmed and tested FPGAs for military radar
system using Xilinx's 3042 library.
EDA TOOLS Verilog-XL, NC Verilog, VCS, Modelsim, Synopsys' Design
Compiler, Verplex, PrimeTime
LANGUAGES Verilog, VHDL, C, Perl, Tcl
EDUCATION MSEE, Boston University, College of Engineering, Boston, MA
BS, Biology, Wesleyan University, Middletown, CT
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