Design Assistant

Sri Ramya Venumbaka

****E, ***S Apt#***, Salt Lake City, Utah-84102

********.*********@****.*** . 903-***-****

Objective:

To seek a challenging entry level position/internship in the field of VLSI/ Semiconductors in a

dynamic and an innovative organization that will utilize my technical and educational background to

the best.

Education:

Master of Science, Electrical Engineering, Graduation: Dec,2010.

University of Utah, Salt Lake City, Utah. GPA: 3.71/4.0

Bachelor of Technology, Electronics and Communication Engineering, Graduation: May, 2008.

Jawaharlal Nehru Technological University, Hyderabad, India. GPA: 3.88/4.0

Technical Skills:

• VLSI Tools: CADENCE- SOC, DRC, LVS and GDS file generation, HSPICE, Virtuoso,

XILINX.

• Scripting Languages: PERL.

• Programming Languages: C, C++, MATLAB, Assembly, Labview, Verilog, VHDL.

• Operating Systems: Windows, LINUX, UNIX, Sun Solaris, Mac OS.

Experience:

University of Utah, Teaching Assistant, August 2010-December 2010.

Responsibilities include preparing Labs for Fundamentals of Electronic Circuits, teaching the students

concepts and skills necessary for successful Lab completion and assisting students when questions

arise. Also, offered Question and Answer (Q&A) Sessions to help students solve Homework related

problems.

University of Utah, Research Assistant, June 2009-August 2010.

Responsible for the characterization of Nano electromechanical switches (NEMS), determination of

best suitable materials for making switches, determine ways of reducing leakage currents, pulse and

AC measurements of these switches and study of the effects of temperature on switching

characteristics. Work also includes design of a piezo sensor circuit to form a switch and determining

its switching characteristics.

Thesis:

• Nano Electromechanical Switches: Thesis work includes measurement of I-V characteristics of

NEMS switches, determination of air gap to reduce the actuation voltages, switching

characteristics, leakage reduction techniques, suitable materials based on melting point and

contact resistance, design of piezo electric circuit and determining the switching properties at

high temperatures.

Projects:

• Vending Machine and VGA Controller: Designed a Vending Machine Controller and VGA

Display Unit. Verilog-HDL is used to verify the functionality of each block and Cadence

simulation tools (Synopsis) are used to draw the gate level design and verify the design.

• SAT Solving for Equivalence Verification: Studied and applied FRAIG technique for effective

SAT solving in Equivalence verification. It deals basically with the equivalence verification of

Combinational circuits with the highly efficient SAT Solvers like MiniSAT and PicoSAT.

• Low Power SRAM Design: Designed a 8 Kbit SRAM using sleep transistors to reduce power

dissipation. 130 nm technology is used to design SRAM cells and HSPICE simulations are used

to determine the optimal number and sizes of transistors in SRAM cells.

• Op-Amp Design: Designed an op-amp that meets particular specifications of power dissipation,

input and output common mode range. The area of the op-amp layout is reduced to the maximum

extent possible.

• 3-bit Flash ADC: Designed a 3-bit Flash Analog to Digital Converter using Sample and Hold

Circuit. The design was extended to 4-bit Flash ADC and it was sent to MOSIS for chip

fabrication. The chip was tested to verify the simulation results and the measured data.

• MAC unit: Designed a high speed 16-bit fused Multiply-Accumulate unit with three main stages

of partial products generation and reduction, partial products addition using carry save adders and

addition of the carry-save result using accumulator.

Graduate Course Work:

Digital VLSI Design, Computer Architecture, Testing and Verification of VLSI circuits, Advanced

Digital VLSI Design, VLSI Architecture, Analog IC Design, Semiconductor Physics.

Accomplishments:

• Presented a paper on ‘ULTRAFAST NANO ELECTROMECHANICAL SWITCHES’ at NANO

UTAH CONFERENCE-2009.

• Selected as Programmer Analyst by Cognizant Technology Solutions in June-2007.

• Received Scholarship awards for academic excellence in High School and under graduation.

• Ranked in the top 25 in National Level Talent Examination, conducted by Unified Council, India.

References available upon request

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