Project Design

Hemant Rathi

**** ********* *****, *****, ** ****9 ? 323-***-**** ? abia9r@r.postjobfree.com

QUALIFICATIONS PROFILE:

. Solid State Processing: Gained knowledge of solid state state-of-the-art

processing techniques including the stages and processes involved in

thermal oxidation, lithography, microlithography, positive and negative

photo-resists, knowledge of different ionic charges, thin film formation

and deposition using CVD and PVD, diffusion, ion implantation and

annealing, metallization. Working knowledge of e-beam lithography and

wafer thinning. Class-room knowledge of statistical process control.

. Solid State Energy devices: Gained knowledge of various aspects of solid

state energy devices including solar cells and LEDs. Various aspects

including production techniques, methods to improve production and

efficiency and minimize area were learnt through software PC1D.

. Computers & VLSI designing tools: Programing in C and C++. Utilize

Windows and Mac based PCs with various softwares: Cadence, HSpice,

Nanosim, Multisim, OrCAD; working with microscopes. Prepare technical

reports and documentation in Microsoft Office (MS Word and Excel). Can

read schematics and complex drawings/diagrams of electronic circuits.

. Key strengths: Finely tuned analytical and research skills with

dedication to clear communication and presentations. Adept at maintaining

an exceptional rate of productivity, accuracy and efficiency; well

organized and proficient with details. Self-motivated, Dependable and

believer of 'Going the Extra Mile'.

EDUCATION:

University of Southern California, Los Angeles, CA

Master of Science, Electrical Engineering (GPA: 3.12/4.0)

May '10

Sardar Vallabhbhai Patel Institute of Technology, Vasad, India

Bachelor of Engineering, Electronics and Communication (GPA: 3.75/4.0)

Jun '08

ACADEMIC PROJECTS:

Silicon Wafer Processing

Spring '10

. Gained 5-months of hands-on experience in working in a class-100 clean-

room with <1-0-0> orientation Si wafer. Various key-steps of wafer

processing were performed including photolithography, wet-etching,

diffusion, oxidation, metallization and sintering. Later, the profile

measurement of different processed components was performed using

LabVIEW.

Critique on a Solar Cell Research Paper

Spring '10

. Wrote a complete analytical critique on a previous research based paper

on Solar Cell titled "High-Efficiency Space & Terrestrial Multijuction

Solar Cells through Bandgap Control in Cell Structures" by et al

Richard R. King.

I2C Bus Interface

Spring '09

. I2C protocol was implemented using Verilog which included applications

like sending/receiving real time data, arbitration and collision

detection and synchronization of clock and data line.

FPGA chip designing

Spring '09

. Designed a program in C for intra-routing and inter-routing between a

pre-defined number of gates on a virtual FPGA board.

Design of 2.048 Kbit SRAM

Spring '09

. Completed design of a transistor level circuit for (128 x 16) SRAM with

precharge circuitry, sense amplifiers, read and write circuitry.

Design of a 'Quarterback' Neural Network

Fall '08

. Completed design and layout of artificial neural net comprising of

digital neurons which detects edges moving from top to bottom of the

network.

WORK EXPERIENCE:

Internship at University of Southern California, Center for Systems &

Software Engineering Jun '10 - Present

. Assisting research scientists at CSSE in architecting a multi-blade

ruggedized mobile server for a research project initiated by US DoD by

analyzing various ruggedized SBC architectures and documenting it.

University of Southern California, Los Angeles, CA

Aug '08 - Feb '10

. Student Worker

Internship at Sahajanand Laser Technology, Ahmedabad, Gujarat, India

Jan '08 - May '08

. Research project based on the use of microcontrollers. This project

designed chips that were used to cut and polish high-end diamonds.

? Available and open to relocate ? Reference available

upon request

Contact this candidate