PRAVESH DANGWAL

****, *** ******, ***# ***, Lubbock, TX 79415 806-***-****

abi9e2@r.postjobfree.com

OBJECTIVE

Seeking a challenging Internship/Full-time position in Semiconductor

Industry.

EDUCATION

Texas Tech University, Lubbock TX

Masters in Electrical Engineering

Expected graduation: December 2010, Current GPA: 3.88

College of Engineering Roorkee, India

Bachelors in Electronics and Telecommunications

Graduated: June 2007, GPA: 3.5

TECHNICAL PROJECTS

Design and Layout of SRAM Texas Tech University, US

. Currently working on this project to design 128 bytes SRAM

(September 10-present)

. Design and layout to be performed using Cadence Virtuoso

Design of Decimal Floating Point Multiplier Texas Tech

University, US

. Designing architecture for decimal floating point IEEE 754 compliant

multiplier (July 10-September 10)

and implementing it using Verilog HDL

. Emulation of design on FPGA and logic synthesis using Cadence RTL

Compiler

Design of simulator for dynamically scheduled CPU Texas Tech University,

US

. Implemented Scoreboard algorithm for dynamic scheduling (September 09-

November 09)

. Used Verilog HDL to design and simulate the algorithm

Simulation of RISC Processor Texas Tech University, US

. Writing behavioral model for RISC processor in Verilog HDL using

Xilinx ISE (September 08-November 08)

. Developed and implemented division algorithm on RISC processor

Three Band Equalizer Design on DSK6713 board Texas Tech University,

US

. Implemented three band equalizer in real time on DSK6713 board.

(January 09-April 09)

. Designed low pass, band pass and high pass filters in MATLAB.

Operational Amplifier Design Texas Tech University, US

. Designed a differential input single ended output operational

amplifier (January 09-April 09)

. Simulated the design on PSpice

Functional Verification and Testing of ADC Texas Tech University,

US

. Written test bench in Verilog and simulation performed on ModelSim

(January 09-April 09)

. Testing of ADC on VLCT and statistical analysis of results

Testing of Static Random Access Memory Texas Tech University, US

. Completed functionality test for SRAM using LabVIEW

(September 08-November 08)

. Used March test for word oriented memories

Simulation of Direct Memory Access (DMA) Controller Centre for

Development of

. Writing behavioral model for DMA using Verilog HDL in ModelSim 6.4

Advanced Computing, India

. Writing test bench for the simulation of model using ModelSim 6.4

(August 06-March 07)

TECHNICAL EXPOSURE

Languages used: C, Verilog HDL, VHDL, assembly 8085, 8086,

Perl

Software tools used: Xilinx ISE, ModelSim, LabVIEW, Cadence RTL

Compiler, Cadence Virtuoso, PSpice

RELATED COURSEWORK

Digital Design, Microprocessor Architecture, Testing of digital systems,

Parametric and Functional Testing, Embedded systems, Solid State Devices,

Design of Analog ICs, Statistics for Engineers.

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