Engineer Design
Resume:
FRANK C. LU
*** ******** ****** #* *******, CA 91007
abhwye@r.postjobfree.com
Delivery through Personal Performance and Leadership
PROFILE
Highly experienced professional with a record of developing and supporting
successful projects and solutions incorporating a wide range of
applications and technologies. Consistently recognized and tasked to
improve organizational effectiveness and efficiency through leadership that
aligns the business processes to realize cost savings, accelerate
performance, and sustain strategic flexibility.
Proven leadership experience in helping build and manage top-performing
business entities with a successful track record of driving quality
improvement, managing efficiency, and positively impacting the corporate
culture and success in strategic planning and contributions to
establishment of company direction.
. Confident, highly energized, effective, and persuasive communicator
with strong interpersonal and communication skills. Detail- and
results-oriented with a proven ability to demonstrate flawless
execution, and implementation of innovative strategies. An analytical
and strategic thinker with the highest professional standards and
personal integrity.
. Highly focused on teamwork and leadership. Well aware of the bottom
line and exceeding both internal and external customers' conditions
for success. Challenges are to be sought out and met, tested against,
and ultimately overcome through hard work and insight gained by making
cost-effective, strategic contributions.
CORE COMPETENCIES
Infrastructure Development . Client Relationship Management . Configuration
Management . Training
Project Management . Team Leadership . Team Development . Semiconductor .
Electronics
Performance Optimization . Process Improvement . Change Management .
Mentoring
PROFESSIONAL EXPERIENCE
Forza Silicon Inc. Pasadena, CA
2006 - 2010
Principal VLSI Design Engineer
Subject-matter expert accountable for the architecture, leading, designing,
and verifying new generation of digital control circuits with flexible
pixel timing and window sizing with ROIC sensors used in defense projects
(0.35um OnSemi).
. Definition, architecture, documentation, RTL design, simulation,
synthesis, gate-level functional verification, floor plan, place and
route, and timing closure on high speed, high-resolution digital
control CMOS imaging sensors (0.18um IBM/Tower). Modeling, RTL design,
simulation, synthesis, place and route, verification, and timing
closure on ADC digital calibration blocks used in high-speed 14 bit
ADCs (0.13um TSMC / 0.18um Tower).
. Lead and architecture Imaging Process Pipeline IP cores and software
used in IBM reference camera system (Xilinx Spartan3 / 6 FPGA based /
Microsoft Windows platform). Functions include dead-pixel correction,
white balance, black-level adjustment, Debayer pattern, color-
correction matrix, and color- lookup tables.
. Successfully managed and architectured a design of 1 Gb+ bandwidth
high-speed camera-data acquisition system (Virtext5 FPGAs based with
DDR2 memory) for in-house characterization and production test use.
Frank C. Lu
Page 2
OmniVision (Aurora Systems) San Jose, CA
2000 - 2006
Senior VLSI Design Engineer
Identified as key leader accountable for the definition, architecture, RTL
design, simulation, synthesis, gate-level logic / timing analysis, and
verification of high speed LCOS CMOS (0.25um / 0.18um TSMC / UMC / Fujitsu
process) driver chips used in projection systems including JVC LCOS HD-ILA
TV. Developed and modeled a color-correction algorithm used with LCOS micro
displays for display enhancement.
. Successfully designed document preparation, lab debug, chip bring up,
chip FIB instructions, AC timing characterization, and performance
tuning for external SDRAM / DDR memory and uLCD device interfaces.
Assist and support system engineer group in PCB schematics, layout,
power consideration, and components selection, and system production
issues.
. Verilog RTL Design, implementation, and functional / logical timing
verification on low-powered design digitalized video stacks,
asynchronous FIFO, I2C master / slave blocks, high bandwidth memory IO
controller, internal SRAM checkers, and internal test-pattern display
generator used in HDTV micro-display devices.
. Researched and documented compression algorithms in improving data
bandwidth demand in high- definition digital micro display devices.
Performed ATPG scan-chain insertion, scan-chain patterns generation,
test-bench designs, debug, and production-test vectors preparation.
. Effectively collaborated with test engineers to bring up wafer and
package test programs and conduct failure analysis and prepare test
reports on RMA-returned devices.
GVC Irvine, CA
1999 - 2000
Hardware Design Engineer
Successfully designed OEM PC motherboards with onboard AGP graphics chip,
LPC I / O controller, PCI Audio circuitry, LAN, and specialized circuitry
required by customers on Intel chipset platforms. Schematics captured with
Orcad / PowerPCB / ECAM tools, and BOM preparation.
EDUCATION
Bachelor of Science, Computer Engineering and Computer Science
University of Southern California Los Angeles, CA
TECHNICAL SUMMARY
C / C++ . Verilog . System Verilog . VHDL . Perl . LISP . Fortran . Java .
Visual Basic . HTML . X86 . Motorola 68000 . MIP assembly languages .
Cadence IUS Design Suite . Cadence RC synthesis . Cadence SOC Encounter
Cadence Conformal . Synopsys Design Compiler . Synopsis Primetime .
Synopsis TetraMax . Mentor Graphics ModelSim . Xilinx ISE . LabWindow .
Power View / View Logic . SPICE
PROFESSIONAL DEVELOPMENT
CEI-Europe Advanced Technology . Advanced Image Sensor Technology course
Advanced Course on CMOS Image Sensors course
PROFESSIONAL CERTIFICATION
Certified Exporter (CE)
LANGUAUGES
English . Mandarin
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