Engineering Design

Zhe Wu

Address: *** ******* **, *** ** West Lafayette, IN 47906

Telephone: 614-***-****

Email: *****@******.***

OBJECTIVE

Seeking a full time position in Electrical and Computer Engineering,

applying previous experience on digital circuit design, verification and

test

EDUCATION

Purdue University, West Lafayette, Indiana

Expected Graduation: December 2014

M.S. Electrical and Computer Engineering

Major GPA: 3.51 (4.00 scale)

The Ohio State University, Columbus, Ohio

Graduation: December 2012

B.S. Electrical and Computer Engineering

GPA: 3.41 (4.00 scale)

WORK EXPERIENCE

Intern

Sep-Dec, 2013

Broadcom, Irvine California, USA

- Worked in Broadband Communications Group (BCG) to develop test bench for

Set-Top Box by using Cyclic Redundancy Checking (CRC)

- Developed several Bash scripts for building test binaries in Linux OS

- Maintained onboard test applications and test websites by C/C++ and

JavaScript in Linux OS

Intern Jun-

Aug, 2012

China Unicom, Harbin, China

- Worked as a system administrator to maintain the mobile carrier's billing

system with Oracle database

- Maintained minicomputer servers, such as HP Superdome 2 in Linux OS

- Supported technology help for the operation department

ENGINEERING PROJECTS

System-on-Chip (SOC) Design

Aug-Dec, 2014

- Implemented the CRC hardware accelerator using Avalon Memory-Mapped

(Avalon-MM) port based on the original IEEE 802.11b "Wi-Fi" MAC protocol

and imported it to Nios II SoC system

- Optimized the CRC Custom Instruction Design performance by implementing

Multi-cycle variable latency scheme.

- Utilized Verilog and C/C++ to Implement the high efficient JPEG decoder

on DE2-115 board by Altera Quartus II, Nios II, QSYS and Modelsim

MOS VLSI Design

Aug-Dec, 2014

- Designed the basic library and utilized it to implement schematic and

layout of an 8-bit Wallace Tree Multiplier with unbalanced pipeline

technology

- Optimized the design by classical methods without CAD generation

Digital Logical System Design

Jan-May, 2014

- Utilized the basic DPLL algorithm and the optimized Chaff efficient BCP

algorithm to implement a Boolean Satisfiability Solver (SAT)

- Optimized the high efficient SAT with parallelization technology on

multi-core computers

Embedded System Jan-

May, 2013

- Utilized MSP430F5438 experimenter board from Texas Instruments to

implement Timer management, configuration of serial peripheral interface

and analog to digital converter

- Utilized language C to implement maze traversal and "mine" detection

program on iRobot

Parallel Programming Jan-

May, 2013

- Utilized OpenMP and OpenCV libraries to modify a mosaic C++ program with

parallel programming technology on a 64 cores Linux machine

- Optimized the parallel program to make it running on AMD 32-core

computer.

HDL Design and Verification

Aug-Dec, 2012

- Utilized Modelsim to design ALU, Finite State Machine and verify the

Floating Point, SEC/DED adder on Altera's ASIC MAX 7000s by VHDL

- Built test bench and scripts program to analyze and verify the design

Contact this candidate