Engineer Process
Resume:
Seung Jin Lee, M.S.
Summary of Qualification
Key Words: Semiconductor FEOL & BEOL Process & Integration, Cu, Al, Low-k,
ULK, BD, BDi, SiCOH, p-SiCOH, LTO, HM TEOS, SiC, SiCN, Aurora, FSG, Coral,
SOD, SilK, PECVD, Thin Film, Dielectric, IMD, Passivation, SOG, HDP, STI,
CMP, Gapfill, Dual Damascene, Planarization, Air gap, 45nm, 65nm, 90nm,
130nm, Flash, SRAM, Failure Analysis, AMAT Producer, ASM Eagle-10, SEM, FIB
Solid Fundamental Knowledge: Semiconductor FEOL & BEOL processes, Cu/Low-k
module process & integration, Cu/Low-k dual damascene process, Low-k
dielectrics unit process, ULK dielectrics unit process, PECVD process, SOG
process, SOD process, Gap fill process, Thin film process, Passivation
process, CVD process, CMP process, STI process, Al Metalization process,
Low-k SOG synthesis, Air gap process, SEM, Failure analysis, Defect
management, Yield management
H/W Set-up: AMAT Producer(BDi Low-k, p-SiCOH, LTO, HM TEOS, SiCN), Hitachi
S-5200 Low Energy SEM for Low-k, ASM Eagle-10(Aurora 2.7(low-k), Aurora
2.4(ULK), SiC, SiCN)
Analysis Tools: Scanning Electron Microscopy (SEM), Focused Ion Beam (FIB),
Nanoindenter(hardness measurement), Micro manipulator 6200(I-V
measurement), CD SEM, Auger Electron Spectroscopy (AES), Secondary Ion
Mass Spectrometry (SIMS), Flexus (Film Stress Measurement),
Ellipsometer(Thickness and RI Measurement), ?-step (Thickness Measurement),
FT-IR, Dielectric Analyzer (DEA), Mercury C-V(K value measurement),
Education
MS in Advanced Material Engineering, KAIST, Daejun, Korea
1995-1997
- Synthesis of low dielectric constant SOG for IMD
BS in Chemical Engineering, Kyung Hee University, Suwon, Korea
1989-1994
Professional Experience
Silver Brook Research, (www.silverbrookresearch.com)
Sydney, Australia
Failure Analysis Engineer, Reliability & Failure Analysis Group
02/2007 - Current
- Failure analysis of ink jet printhead using optical stereo microscope,
SEM, liquid crystal, comet electrical tester.
- Epoxy potting, cross sectioning and polishing of CMOS die.
- Optical microscope and SEM inspection for CMOS die.
- Electrical test of CMOS/MEMS die.
- Liquid crystal hot spot detection analysis for electrically failed die.
- Print test for failure analysis of printehead.
- CMOS die crack analysis
- MEMS mechanical damage analysis
- Wire bonding failure analysis
- Ink ingression to encapsulant analysis
- PCB Cu stack analysis
- CMOS BPSG damage analysis
Samsung Electronics (SYS. LSI Division), (www.samsung.com)
Giheung, South Korea
Manager (Senior Engineer), BEOL Thin Film Development, Advanced Process
Development, 08/2001 - 01/2007
> Responsible for BEOL thin film process & Low-k module integration of all
Samsung SYS. LSI's new technologies and products (SiCOH, p-SiCOH, LTO, TEOS
HM, SiCN, Aurora 2.7, Aurora 2.4), ranging from 130nm to 45nm node,
focusing on Cu/Low-k & Cu/ULK interconnect processes.
> Strong cross-functional interaction across unit process, module process,
integration and manufacturing
Technical Roles
- Development of new BEOL thin film & Low-k process (BDi, SiCOH, p-SiCOH,
LTO, TEOS HM, Aurora2.7 low-k thin film, SiCN) focusing 45nm and beyond.
- Integration of BEOL Cu/low-k module process focusing 45nm and beyond
- Problem solving for BEOL thin film related integration issues
- BEOL thin film CVD tools(AMAT producer, ASM Eagle-10) set-up for 45nm and
beyond
- Physical failure analyses and root cause identification for BEOL module
process & ET yield improvement
- Low-k SEM(Hitachi S5200) set-up and running for 65nm and beyond low-k
BEOL module process and integration
Managerial Roles
- Close interaction with unit process development, integration and
production for fast and effective development of new processes and
resolution of process related issues in development and early production
stages
- Manage a small BEOL thin film process development group and supervise
BEOL Cu/Low-k module integration for 45nm and beyond.
- Co-work w/ reliability group for BEOL reliability improvement
- Plan and supervise new FAB's BEOL thin film tool set-up for 45nm and
beyond.
- Selection and purchase recommendation of BEOL thin film process equipment
- Benchmarking leading semiconductor company's BEOL Cu/Low-k module process
development
HYNIX (Memory R&D div), (www.hynix.com)
Ichon, South Korea
Engineer, Thin Film Development, Process Development,
01/1997 -07/ 2001
- Supervise advanced BEOL thin film process for below 250nm and beyond
Flash & SRAM.
- Development of BEOL Low-k SOG Thin Film process for below 250nm and
beyond DRAM, Flash & SRAM.
- Development of advanced BEOL thin film process (SOG etch back, HDP, SROX)
for below 250nm and beyond DRAM, Flash & SRAM.
- Development of advanced FEOL thin film process (BPSG, FSG, HDP CMP) for
below 250nm and beyond DRAM, Flash & SRAM.
- Development of FEOL SOG process for below 250nm and beyond DRAM
- Development of CMP process(STI CMP, HDP IMD CMP, IPO BPSG CMP) for below
250nm and beyond Flash & SRAM.
- SOG coater (TOK) set-up for BEOL thin film development.
Professional Societies & Activities
- Senior member of IEEE (Institute of Electrical and Electronic Engineers).
- Member of Electron Devices Society (EDS)
Patents
US Patent
1. "Method for Forming a Spin-on-Glass layer", Seung Jin Lee; US6313044B1
2. "Semiconductor device including trench isolation structure and method of
forming the same" Dong Suk Shin; Seung Jin Lee; Young Kuk Jeong; ki Kwan
Park; US2007/0059898A1
3. "Method for Forming dual damascen wiring for semiconductor device using
protective via capping layer", Jae Hak Kim; Sun Jung Lee; Seung Jin Lee;
US2006/0178002A1
4. "Method for Forming interconnection lines for semiconductor device",
Kyung Woo Lee; Hong Jae Shin; Jae Hak Kim; Young Jin Wee; Seung Jin Lee; Ki
Kwan Park; US2005/0176236A1
5. "Method for Forming interconnection lines for semiconductor device and
interconnection line structure", Kyung Woo Lee; Hong Jae Shin; Jae Hak Kim;
Young Jin Wee; Seung Jin Lee; Ki Kwan Park US2005/0161821A1.
6. "Method for Forming interconnection lines for semiconductor device",
Kyung Woo Lee; Hong Jae Shin; Jae Hak Kim; Young Jin Wee; Seung Jin Lee; Ki
Kwan Park; US7192864B2
7. "Method for Forming a Spin-on-Glass Thin Film", Seung Jin Lee;
Application No. 09/364330
8. "Method of Manufacturing a High Density Plasma Oxide Thin Film", Seung
Jin Lee ; Application No. 09/345301.
9. "Method of fabricating printing assembly", Seung Jin Lee; PRE056US
10. "Molded ink manifold with polymer coating", Seung Jin Lee; Susan
willams; Jan Waszczuk; PRE055US
Japan Patent
1. "Method for Forming a Spin-on-Glass Thin Film", Seung Jin Lee;
JP2000138214
2. "Method for Forming a Spin-on-Glass Thin Film", Seung Jin Lee;
JP3554686B2
3. "METHOD FOR MANUFACTURING DUAL DAMASCENE WIRING OF SEMICONDUCTOR ELEMENT
USING VIA CAPPING PROTECTION FILM" Jae Hak Kim; Sun Jung Lee; Seung Jin
Lee; JP2006028750
4. "METHOD FOR WIRING IN SEMICONDUCTOR ELEMENT AND WIRING STRUCTURE" Kyung
Woo Lee; Hong Jae Shin; Jae Hak Kim; Young Jin Wee; Seung Jin Lee; Ki Kwan
Park JP2005217412
5. "Method of Manufacturing a High Density Plasma Oxide Thin Film", Seung
Jin Lee; Application No. 11-185467
Korea Patent
1. "Method for Forming a Spin-on-Glass Thin Film" Seung Jin Lee; KR10-
2. "Method for forming metal line semiconductor device" Seung Jin Lee; KR10-
3. "METHOD FOR REMOVING MICRO SCRATCHING IN DIELECTRICLAYER OCCURRING BY
CHEMICAL MECHANICAL POLISHING ANDMETHOD FOR FORMING ISOLATION LAYER USING
THE SAME" Seung Jin Lee ; KR10-0650711-0000
4. "Method for forming organic-oxide layers stack and interconnection
wiring structure" Seung Jin Lee; KR10-2006-0040858
5. "Method of forming an interlayer insulating film in semiconductor
device" Seung Jin Lee; Sang Bum Kim; KR10-0328456-0000
6. "Method of forming a SOG film in a semiconductor device" Sun Woo Kim;
Seung Jin Lee; KR10-0297106-0000
7. "SOG CHEMICAL COMPAUND FOR PLANARIZING A SEMICONDUCTOR DEVICE AND METHOD
OF MANUFACTURING THE SAME" Seung Jin Lee; Sun Woo Kim; KR10-0293630-0000
8. "METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE" Sun Woo Kim; Seung Jin
Lee; KR10-0440264-0000
9. "METHOD FOR FORMING METAL INTERCONNECTION LAYER IN SEMICONDUCTOR DEVICE"
You Suk Soe; Seung Jin Lee; KR10-0353534-0000
10. "Trench isolation methods of semiconductor device" Dong Suk Shin; Seung
Jin Lee; Young Kuk Jeong; ki Kwan Park; KR10-0746223-0000
11. "Method of forming a via contact structure using a dual damascene
process" Kyung Woo Lee; Hong Jae Shin; Jae Hak Kim; Young Jin Wee; Seung
Jin Lee; Ki Kwan Park; KR10-2005-0116479
12. "Method of forming interconnection line in semiconductor device" Kyung
Woo Lee; Hong Jae Shin; Jae Hak Kim; Young Jin Wee; Seung Jin Lee; Ki Kwan
Park; KR10-0576367-0000
13. "Method of forming interconnection line and interconnection line
structure in semiconductor device" Kyung Woo Lee; Hong Jae Shin; Jae Hak
Kim; Young Jin Wee; Seung Jin Lee; Ki Kwan Park KR20050077457
14. "Method of forming interconnection line and interconnection line
structure in semiconductor device" Kyung Woo Lee; Hong Jae Shin; Jae Hak
Kim; Young Jin Wee; Seung Jin Lee; Ki Kwan Park; KR10-0593737-0000
15. "Fabrication method of dual damascene interconnections of
microelectronics and microelectronics having dual damascene
interconnections fabricated thereby" Jae Hak Kim; Sun Jung Lee; Seung Jin
Lee KR10-0690881-0000
Taiwan Patent
1. "Method for Forming a Spin-on-Glass Thin Film", Seung Jin Lee; TW425620B
2. "Method of Manufacturing a High Density Plasma Oxide Thin Film", Seung
Jin Lee; Application No. 88111056
Europe Patent
1. "Interconnection structure and method of forming same" Kyung Woo Lee;
Hong Jae Shin; Jae Hak Kim; Young Jin Wee; Seung Jin Lee; Ki Kwan Park
EP1560264
China Patent
1. "Method for forming interconnection line in semiconductor device and
interconnection line structure (Method for forming interconnection line in
semiconductor device and interconnection line structure)" Kyung Woo Lee;
Hong Jae Shin; Jae Hak Kim; Young Jin Wee; Seung Jin Lee; Ki Kwan Park;
CN1649126
2. "Method for forming interconnection line in semiconductor device and
interconnection line structure (Method for forming interconnection line in
semiconductor device and interconnection line structure)" Kyung Woo Lee;
Hong Jae Shin; Jae Hak Kim; Young Jin Wee; Seung Jin Lee; Ki Kwan Park;
CN100349281C
Publications & Presentations
Conference Paper
1. "A Low Dielectric Constant Spin-on-Glass for Interlevel Dielectrics",
The Polymer Society Korea, (1997).
2. "A Low Dielectric Constant Spin-on-Glass for Interlevel Dielectrics",
Seung Jin Lee; Jae Young Kim; Jin Baek Kim; Dong Ho Lee; Yeon Su Kim; Chol
Mo Jung; Sang Bum Kim; Pyeong Gun Son; Han Min Kim; Hong Sun Yang;
Dielectric/Conductors for ULSI Multilevel Interconnect Conference, (2001).
3. "Cost-Effective "BARC/Resist_Via_Fill Free" Integration Technology for
0.13um Cu/Low-K", Soo-Geun Lee; Kyoung-Woo Lee; Il-Goo Kim; Wan-Jae Park;
Young-Jin Wee; Won-Sang Song; Jae-Hak Kim; Seung-Jin Lee; Hyeok-Sang Oh;
Yong-Tak Lee; Joo-Hyuk Chung; Ho-kyu Kang; Kwang-Pyuk Suh IEDM, (2002).
4. "A HSQ Based Inorganic Sacrificial Via Filler-assisted 90nm-node Cu/Low-
k OSG Dual Damascene Process Integration", Lee, K.-W.; Lee, S.G.; Park,
W.J.; Oh, B.J.; Kim, J.H.; Seung Jin Lee; Park, K.K.; Kim, I.G.; Chung,
J.H.; Lee, K.T.; We, Y.J.; Song, W.S.; Hah, S.R.; Kang, H.-K.; Suh, K.-P.
VLSI, (2003)
5. "Alleviating Electromigraion Through Re-engineering the Interface
Between Cu & Dielectric-Diffusion-Barrier in 90nm Cu/SiOC(k=2.9) Device",
Young Jin Wee; Soo Geun Lee; Won Sang Song; Kyoung-Woo Lee; Nam Hyung Lee;
Ja Eung Ku; Ki-Kwan Park; Seung Jin Lee; Jae Hak Kim; Joo Hyuk Chung; Hong
Jae Shin; Sang Rok Hah; Ho-Kyu Kang; Gwang Pyuk Suh; IEDM, (2003)
6. "Highly manufacturable Cu/Low-k dual damascene process integration for
65nm technology node", Lee, K.-W.; Shin, H.J.; Hwang, J.W.; Nam, S.W.;
Moon, Y.J.; Wee, Y.J.; Kim, I.G.; Park, W.J.; Kim, J.H.; Seung Jin Lee;
Park, K.K.; Kang, H.-K.; Suh, K.-P. IITC, (2004)
7. "Electromigration Failure Mechanism and Lifetime Expectation for Bi-
Modal Distribution in Cu/Low-k Interconnect", Young Jin Wee; Kim, A.T.;
Jung Eun Lee; Jae Yeol Maeng; Woon Hyuk Choi; Seowoo Nam; Seung Jin Lee;
Kyoung Woo Lee; Jaehak Kim; Keeyoung Jun; Seung Man Choi; Jaeouk Choo;
Jungshik Heo; Hong Jae Shin; Nae In Lee; IITC, (2007)
References
1. Andrew Kim (abhtu7@r.postjobfree.com), Reliability Engineering Consultant,
GE Energy
2. Seowoo Nam (abhtu7@r.postjobfree.com), Senior Process Engineer, Advanced
Technology Development Team, Samsung Electronics
3. Sun Woo Kim (abhtu7@r.postjobfree.com), Staff Engineer, Infineon
Technologies
1 Bridge Rd, North Ryde, NSW 2113 Australia
+61-400-***-*** ( abhtu7@r.postjobfree.com
Australian Citizen
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