Design Years Experience

Nancy Lao

San Jose, CA abhs22@r.postjobfree.com 408-***-****

OBJECTIVE

IC Layout/Mask Design

SUMMARY OF QUALIFICATIONS

10+ years experience work with high speed serial interface I/O's and Mixed

Signal Mask Design layout. Organized and planned workload based on

delivery schedule and ensured delivery schedule were met. Partner with CAD

work of run deck verifications for error free layout blocks. Ensure the

quality of layout meet company goal for achieve time to market objectives.

TECHNICAL SKILLS

. Technical Expertise: Detailed implementation floor planning of

various I/O design types with consideration to electro-migration.

Strong knowledge of ESD device, Latch-up prevention, Component

Matching, Block Placement, Routing.

. Technologies: CMOS, 40/45nm, 65nm, 90nm, .12um, .20um, .25um, .35um

. Foundry: TSMC - used up to 8 metal & AP layers

. Software Tools: Cadence Opus Virtuoso, Virtuoso GXL

. Proficiencies: Layout Editor, Schematic Composer, (Calibre, Hercules,

Assura, Dracula & Diva) backend verification check

DRC/LVS/ERC/Antenna/Density

. OS: UNIX, Linux Windows

. Good debugging DRC/LVS skill and knowledge of IO layout circuits.

PROFESSIONAL EXPERIENCE

IBM Almaden Research - San Jose, CA (Solution Design Contractor)

2010 - 2010

. Using latest version of Virtuoso GXL to perform overall

implementation of SRAM

Block included: core memory cell - single/dual port, row and

column decoder, sense amp with specialty on critical current

source, and random read/write control logic. Ran verification

LVS/DRC/ERC/antenna using Calibre/Hercules interface with IBM in-

house tools. Excellent knowledge on ESD and latch-up. Specialty

on SRAM/DRAM, ROM, Register File, and IO pad.

. TSMC, 40nm technology.

NXP Semiconductors (formerly PHILIPS Semiconductors) - San Jose, CA

2006 - 2009

Senior Layout Designer, I/O Development Division

. Accomplished number of I/O libraries for use in many successfully

products.

. Detailed implementation mask design layout work of various type I/O

designs involving 1.2V, 3.3V and 5V tolerances (Power, Ground, Signals

IO, Diode, ESD structures, includes various type of Driver, Predriver

and Inbufs).

. Performed definition and layout of CMOS45 (45nm) LPDDR I/Os.

. Completed layout of the CMOS65 (65nm) SDR/DDR2 combo and LPDDR I/Os

for memory interfaces. These I/Os were also put on the test chip.

. Performed definition and design of I/O layout frame for the CMOS090

(0.09um-50um pitch) technology and populated with 2.5V, 1.8V, analog

I/O, IIC, PCI, power/ground, filler/splitter cells. Completed DDR2

I/Os for 333 MHz, which was silicon proven in many products in this

technology.

PHILIPS Semiconductors - San Jose, CA 1999 -

2006

Senior Layout Designer, I/O Development Division

. Performed high speed serial interface layout including MIPI and sub-

LVDS.

. Performed layout of CMOS12 (0.12um - 35um pitch) Philips technology

I/Os in 3.3V, 2.5V flavor, PCI, IIC, power/ground, splitter, and

filler cells. Qualified design layout using cleanup and verification

scripts.

. Performed layout of I/O frames for the Tall frame (pad limited - 40um)

and Short frame (core limited - 70um) in .18um CMOS18 Philips

technology (high-Res substrate). Made modular sub-cells for reuse in

building all I/Os including 3.3V, 2.5V, PCI, 5V - tolerant, IIC. Ran

through various abutments and verification checks to ensure the

quality of the I/O library.

. Performed layout of UniNorth 1.5 and received recognition from the

Apple Sales Team for contributions.

. Completed I/O frame design for 0.15um process and created layouts for

3.3V I/Os, PCI, analog I/Os, and 5V tolerant.

. Provided maintenance and supported I/O layout on 0.35um, 0.25um and

.20um technologies.

VLSI Technology - San Jose, CA 1996 -

1999

Layout Designer

. Performed layout of Standard Cells, SRAM, Memory and I/O Cells on

0.35um, 0.25um and .20um technologies.

EDUCATION

. HS Diploma - Vietnam

. Institute for Business & Technology - Santa Clara, CA

Diploma: CMOS Layout Design

. Cadence, Inc. - Santa Clara, CA

Certificate of Achievement: Virtuoso Custom Layout & Interactive

Verification

. De Anza College - Cupertino, CA

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