Engineer Manager
Resume:
Thomas G. Mallon
Santa Clara, CA *****
**.******@*********.***
SUMMARY:
Registered Patent Attorney, experienced in drafting responses to Office
Action, appeals, and patent applications. Extensive experience as an
engineer and manager in semiconductor process development and
manufacturing. Inventor on eleven (11) U.S. patents.
CERTIFICATIONS:
Admitted to the State Bar of California - Bar Registration No. 267,908
Admitted to practice before the United States District Court, Northern
District of California
US Patent and Trademark Office - Registration No. 66,649
EDUCATION
Santa Clara University School of Law, Santa Clara, CA
Juris Doctor, May 2009
Emphasis: Intellectual Property Law
Honors: Recipient, Emery Merit Scholarship
San Jose State University, San Jose, CA
BS in Materials Engineering, Cum laude
Second Major in Environmental Studies
Honors: Dean's List; Phi Kappa Phi
PROFESSIONAL EXPERIENCE
Shemwell Mahamedi LLP, San Jose, CA, Patent Engineer 2007 to
2009
. Performed legal research, wrote USPTO Office Action responses and Appeal
Briefs, and drafted patent applications.
. Reduced hours worked per USPTO Office Action by designing an Office
Action checklist.
Sipex, Inc., Milpitas, CA, Staff Process Engineer
2002 to 2006
. Developed and sustained Wet Etch and Plasma Etch processes in analog IC
wafer fab.
. Enabled a circuit design geometry-shrink by developing improved etch
processes.
. Reduced mis-processing and contributed to successful ISO 9001
registration of the wafer fab by creating or revising documentation
needed for employee training and for process transfer.
. Enabled significant wafer manufacturing cost reduction by transferring
etch processes to foundry partner in Hangzhou, China.
Silicon Genesis Corp. San Jose, CA, Manufacturing Control Manager
1998 to 2002
. Managed materials planning, shipping, data control, and document control
for a start-up company producing engineered semiconductor substrates.
. Managed successful ISO 9001 re-registration of manufacturing processes.
. Managed processing equipment installations and performed process
development.
. Developed first-of-its-kind process for backside laser scribing of
silicon wafers.
Lam Research Corp., Fremont, CA, Process Applications Manager
1995 to 1998
. Managed customer demonstrations of Lam's CMP (chemi-mechanical
planarization) tool.
. Managed field process support for CMP systems installed in US, Asia, and
Europe.
. Achieved 20% reduction in non-uniformity of CMP process by modifying
Lam's CMP tool. The modification was later patented.
Thomas G. Mallon
Santa Clara, CA 95051
**.******@*********.***
PROFESSIONAL EXPERIENCE (continued)
LSI Logic Corp., Santa Clara, CA, Senior Process Development Engineer
1988 to 1995
. Developed Plasma Etch and CMP processes for sub-micron CMOS ASIC's.
. Transferred pilot-line CMP process to production facility in Tsukuba,
Japan, enabling LSI Logic to mass-manufacture the microprocessor for
Sony's PlayStation.
. Submitted invention disclosures that resulted in ten (10) U.S. patents.
. Sustained Plasma Etch processes in a small fab dedicated to processing
CMOS ASIC products for a U.S. government contract. Held DoD Top Secret
Clearance.
AFFILIATIONS
. Member of the American Intellectual Property Law Association
. Member of the Silicon Valley Intellectual Property Law Association
. CMP Users Group of the NCCAVS: Co-founder - 1995; Secretary - 1996;
Chairman - 1997
ADDITIONAL INFORMATION
U.S. Patents (Inventor or Co-inventor):
# Patent No. # Patent No. # Patent No. # Patent No.
1 #6,109,775 4 #5,719,084 7 #5,624,304 10 #5,310,455
2 #5,876,838 5 #5,667,433 8 #5,516,400 11 #5,278,103
3 #5,722,877 6 #5,628,869 9 #5,362,353
Publications & Presentations
1. T. Mallon, Performance of Linear Planarization Technology, Proc. 3rd
International CMP Symposium, Dec. 1, 1997, pp. 265 - 85.
2. T. Mallon, OnTrak's Linear Planarization Technology, Proc. CMP Users
Group, vol. 2, no. 3, Sept. 1997, pp. 57 - 72.
3. T. Mallon, K. Mishra, & R. Jairath, Pattern Density Effects: A
Comparison of Linear CMP and Rotary CMP, Proc. 2nd CMP-MIC, Feb. 13 - 14,
1997, pp. 173 - 76.
4. R. Jairath, S. Chadda, E. Engdahl, W. Krusell, T. Mallon, K. Mishra, A.
Pant, & B Withers, Performance of OnTrak Systems' Linear Planarization
Technology (LPT) for Dielectric CMP Processes, Proc. 2nd CMP-MIC, Feb. 13
- 14, 1997, pp. 194 - 201.
5. I.J. Malik, T. Mallon, B. Withers, R. Emani, D. Mordo, & I. Goswami, CMP
of FSG: Issues in Process Integration, Proc. 2nd CMP-MIC, Feb. 13 - 14,
1997, pp. 209 - 12.
6. D. Mordo, I. Goswami, I.J. Malik, T. Mallon, B. Withers, & R. Emani,
Characterization of PECVD Deposited Fluorosilicate Glass (FSG) After CMP
and Cleaning, Low Dielectric Constant Materials II, vol. 443, Proc. Fall
1996 MRS Meeting, Dec. 1996, pp. 127 - 35.
7. T. Mallon, K. Mishra, & R. Jairath, Within Die Non-uniformity: A
Comparison of Linear CMP and Rotary CMP, Proc. 1st Annual Symposium, CMP
Users Group, Nov. 1996, pp. 96 - 105.
8. R. Jairath, A. Pant, T. Mallon, B Withers, & W. Krusell, Linear
Planarization for CMP, Solid State Technology, Vol. 39, No. 10, Oct.
1996, pp. 109 - 12.
9. T. Mallon, Metrology for CMP, Proc. CMP Users Group, vol. 1, no. 3, Oct.
1996, pp. 131 - 33.
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