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Design System

Location:
San Jose, California, 95133, United States
Posted:
March 09, 2011

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YAN JIAO

**** ***** **, *** ****, CA, *****

(408)***-****

abhrg5@r.postjobfree.com

OBJECTIVE:

Seeking a challenging position related to FPGA/Hardware/IC Design or

Verification.

QUALIFICATION:

< Skill in ASIC/FPGA design, including architecture design,

specification writing, RTL coding, functional simulation, system

synthesis, timing analysis, DRC & LVS verification, and FPGA

implementation.

< Good CPU architecture/micro-architecture knowledge (MIPS/ARM

architectures, pipeline, cache).

< Proficient in coding RTL using Verilog and VHDL.

< Experience in ARM, DLX (RISC) Microprocessor Architecture and AMBA Bus

Architecture.

< Strong background in Embedded System Design.

< Familiar with VLSI design, combinational, sequential circuit design,

and memory design.

< Comfortable working on C, Perl, TCL and Assembly Language.

EDUCATION:

M.S. in Electrical Engineering May 2010 Polytechnic Institute of New York

University, Brooklyn, NY GPA: 3.9/4

B.S. in Electrical Engineering July 2008 Dalian Maritime University,

China GPA: 3.3/4

EXPERIENCE:

DLX-based Microprocessor (Verilog/ Modelsim, Xilinx Spartan 3E)

02/2010 -- 05/2010

< Developed system functions, specifications and architecture of the DLX-

based processor using Verilog.

< Synthesized the RTL code on Xilinx Implementation tools.

< Performed functional and timing simulation of the codes with Modelsim.

< Designed testbench for functional verification by generating stimulus

and tester.

< Set a clock delay locked loop with DCM.

< Created the user constraints and generated the programming file using

Xilinx ISE.

< Trigged the internal signals of the design inside a Spartan 3E FPGA with

Chipscope.

< Placed and routed the design to XILINX FPGA - Spartan 3E with critical

path delay 12.072ns.

Real Time Embedded System Design-Home Automation System (VHDL/Modelsim/ISE)

09/2009 -- 12/2009

< Involved in planning, designing, and developing of an embedded system--

an electronic home automation system controller which can control

various devices such as audio, temperature, home security, door

automation, and Bluetooth capabilities.

< Established the CPU based on the ARM7 architecture. It consists of

Instruction Decoder & Control logic, Data Register, Address Register,

ALU, Address Incrementer, Register Bank, Comparator, and Barrel Shifter.

< Accomplished the bus module by referring the AMBA AHB bus protocol.

< Implemented the Memory mapped-I/O in the design.

< Generated the assembly code for security system, temperature control,

garage door control, and Bluetooth interface.

< Mapped the whole design to XILINX FPGA-- Vertex 5 LX110T with critical

path delay 6.804ns.

Unwrapper for HPC/NOC (VHDL/ Modelsim, Xilinx)

03/2009 -- 05/2009

Graduate Assistant

< Brainstormed and schemed out the Unwrapper in VHDL by referring AMBA

AHB specification.

< Designed the Unwrapper to assemble the compressed data that were

original too large to be transmitted at one time via the bus.

< Verified the operation of the design by performing functional

simulation with Modelsim.

Advanced Computer Hardware Design (Verilog/ Modelsim, Xilinx)

09/2008 -- 12/2008

< Created design flows, and coded in Verilog for Grain and RC5.

< Integrated all the RTL modules and created system level tops.

< Performed functional and timing analysis of the codes by using

Modelsim.

< Synthesized the modified RTL codes on Xilinx Implementation tools.

< Mapped the above projects to XILINX FPGA - Spartan 3E using Place and

Route (ISE tool).

Implementation of a 16-bit Modified Booth Multiplier (CADENCE)

09/2008 -- 12/2008

< Implemented a 16-bit Modified Booth Multiplier with Booth-based

algorithm and Wallace Tree in CADENCE.

< Designed transistor level schematic for 8 partial product generators

(each consists of one Booth Encoder and 16 Selectors), 16 compressors,

and 33 Wallace trees.

< Executed circuit simulation for the whole design.

< Performed and verified the layout of the multiplier using Cadence

tools.

< Checked the functionality of the design with its extracted view in

Cadence.

< Run DRC & LVS verification to confirm that the design was meeting the

fabrication requirements.

COURSES:

Computer Architecture II

Real Time Embedded System Design

Advanced Computer Hardware Design (VHDL)

Introduction to VLSI

Select Topic in Computer Device & System

Programming with C

Computer Principles and Applications

Principles Database System

Principles of Communication Network

Internet Architecture & Protocol (TCP/IP)

KEYWORDS:

ASIC/FPGA, HARDWARE, CPU, VERILOG, VHDL, C LANGUAGE, PERL, TCL



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