Design Engineer

Terry Jackson Sr., Home: 303-***-****, Cell: 303-***-****, Email:

abhqqi@r.postjobfree.com

PROFESSIONAL FIELDS

- Programmable Logic - HDLs: VHDL, Verilog,

Design/Verification SystemVerilog

- Verification of FPGAs via PCI - Digital Filter Design,

Emulator Test Bench Test Bench Design

- ASIC Verification with - RTL/Behavioral

Front-End Design Experience Architectural Code Design

EDUCATION, SPECIAL TRAINING AND AWARDS

- Denver Technical College; Denver, CO; Course Major: Computer Engineering

- Laney Metro College; Oakland, CA; Course Major: Electronic Engineering,

BSEE (pending)

- Synopsys Chip Synthesis Workshop; Sunnyvale, CA

- Synopsys Intro to Primetime Static Timing Analysis Workshop; Sunnyvale,

CA

- Synopsys Formality Verification Workshop; Sunnyvale, CA

- Mentor Graphics Design-for-Test: Scan and ATPG Workshop; Longmont, CO

- KnowledgeTek Disk Drive Technology Workshop; Longmont, CO

- MEI Technologies, Inc.; LMSSC ASRG Program Award of Excellence For FPGA

Development Work

- Rela, Inc.; Certificate of Appreciation on Projects GEMINI, CACTUS and

IBERIS

- Infineon Technologies, Inc.; Certificate of Appreciation For ASIC

Verification on Project LAGUNA

WORK EXPERIENCE

25 years of combined experience in ASIC front-end and programmable logic

design and verification.

Relevant Tools: Xilinx ISE, ModelSim, HDL Designer, ACTEL Designer,

Synplify Pro, Matlab/Simulink

Devices: RTAX ProASIC+ (APA1000 1Mega gates FPGA) and Axcelerator (AX2000

2Mega gates FPGA)

6/2007 - 12/2009: FPGA Designer, Lockheed Martin through MEI Technologies,

Inc. Littleton, CO

. ASRG Project (Advanced Stirling Radioisotope Generator)

o Designed system level VHDL test bench, instantiated three controller

FPGA's at the top level

o Written all VHDL test bench components and force files for timing

and stimulus generation

o Verified both RTL functional and back-annotated timing simulations

o Designed/written VHDL code for critical fault detection sub-module

block for controller FPGA

o Verified all FPGA functionality against the DDD (Design Description

Document)

o Waveform signal analysis was the verification method

o Reported and fixed design bugs when identified.

Attended/participated in all CDRs as needed

. JUNO Project C&DH (Control and Data Handling) PCI Emulator Test Bench

(Voyager PCI Bridge)

o Updated PCI test bench architecture to accommodate new asynchronous

serial FPGA verification

o This component is one of three FPGAs incorporated on the DTCI-J card

electronics

o Written code for all test bench components, test scripts, text

files, compile and simulation scripts etc

o Verified both RTL functional and back-annotated timing simulations

o Verified all FPGA functionality against the DDD (Design Description

Document) via LB interface

o Reported and fixed RTL design bugs when identified.

Attended/participated in all CDRs as needed

o Waveform signal analysis was the verification method with some self-

checking features

o Conducted verification testing with interfaces to flight hardware

(LB and PCI bus interface)

o Voyager PCI Bridge FPGA recursive verification on both RTL and back-

annotated files

. GRAIL Project C&DH (Control and Data Handling) PCI Emulator Test Bench

(Enterprise PCI Bridge)

o Updated PCI test bench architecture to accommodate new asynchronous

serial FPGA verification

o This component is one of three FPGAs incorporated on the DTCI-G card

electronics

o Test bench was design/architect with major differences from the JUNO

version

o FPGA contained less asynchronous serial ports pulse FLASH memory

controller module block

o Test bench requires FLASH memory models for the verification of the

internal FLASH controller

o Written code for all test bench components, test scripts, text

files, compile and simulation scripts

o Verified both RTL functional and back-annotated timing simulations

o Verified all FPGA functionality against the DDD (Design Description

Document) via LB interface

o Reported and fixed RTL design bugs when identified

o Waveform signal analysis was the verification method with some self-

checking features

o Conducted verification testing with interfaces to flight hardware

(LB and PCI bus interface) Verified MFB (Multi-Functional Block)

logic module to assure that signals are properly synchronized across

clock domains (24MHz and 33MHz). Attended/participated in all CDRs

as needed

2005 - 2007: FPGA Firmware Contractor

. Performing ASIC/FPGA front-end firmware development for a variety of

customers

2005: FPGA Firmware Engineer, Quest Product Development, Wheat Ridge, CO

. FPGA/CPLD firmware (Verilog) development work for Armstrong II DC Motor

Control Module: Improved SPI internal support logic.

. Tools used: Quartus II v4.2 SP1

1999-2003: ASIC Design Engineer; Infineon Technologies, Longmont, CO

. Responsible for VHDL/Verilog RTL behavioral code development for HDC

(Hard Disk Controller) ASIC front-end design and design verification

process.

. Development effort was automated through Perl scripts that linked the

design units with the ASIC development tools through a UNIX C-shell

environment.

. Responsible for design and design verification of all modules assigned

including test benches etc.

. Tools and languages used:

VHDL/Verilog HDL, C/C++, Specman eHVL, Tcl, Perl, Design Compiler,

PrimeTime STA, ModelSim, Cadance NC, Formality, Debussy, Verification

Navigator and Clearcase Version Control System.

1999: Digital Design Engineer, Omnitech Robotics, Englewood, CO

. Support circuit designs, test and debug of LRU modules (line-replaceable-

units) for standardized robotics systems. Each module contained an

AT80C592 custom CANIO board which consisted of an Atmel AT40K20 FPGA,

data acquisition, Flash/SRAM memory, power converter, digital/analog and

communication I/O ports (SPI, II2C, RS232).

. Involved in the design of the PSU (power-supply-unit) logic and power

management circuits. Partially responsible for the SRT (safety-radio-

transmitter) design for emergency shutdown of the vehicle.

. Designed the NiMH battery charger and gas gage monitor plus all the

digital logic for this AT89S8252 based module.

. Supported the team with VHDL design synthesis/simulation and graphic

design entry using Viewlogic Workview Office development tools and the

Atmel FIGARO FPGA IDS. Responsible for investigating and leaning new

development tools and device technology, such as Xilinx's Foundation

Tools and devices.

. Designed and maintained three VHDL modules: SPI, address decoder with

complex bank switching logic for Flash SRAM and the 4 channel PWM module.

. All hardware debug and testing was performed through an 8051 ICE with

assembly language instructions.

. Performed schematic design, BOM generation and created support

documentation.

1996-1999: Digital Design Engineer, Kentek Information Systems, Boulder, CO

. Up-date an exiting design (Motorola 68301 base board) to interface with

two stepper motor servo controllers (by SERVEX), HCIMF interface port and

provide circuitry for monitoring environmental conditions within the

printer.

. Integrated an FPGA and ISP CPLD design implementation into the unused

processor address space, located on the PCB.

. Designed the analog signal conditioning circuitry for monitoring Ambient

Temperature, Barometric Pressure and Relative Humidity.

. Design/Sustain engineering support of an Embedded Pentium II ATX

motherboard, custom PCI cards API (ATX Power Interface), MFIO (Multi-

Function I/O) and associate daughter boards (Video40DX and Expansion

Board (SCSI interface)). Architecture design support and hardware debug

of the DMA bus arbitration timing between the PCI Bridge and Data

Compression/Decompression IC and the i960CA embedded controller via data

transfers to DRAM.

. Responsible for the schematics and logic equations updates combinatorial

and state sequential. Involved in all levels of system bus timing and

drive analysis etc. Integrated all SCSI logic onto the MFIO board and

designed new SCSI controller uP bus interface logic written in VHDL,

implemented in an Altera CPLD and synthesized using MAX+II.

Terry Jackson Sr. Page 3

. Ability to read and interpret driver level C/C++ programs. Generated the

necessary documentation for software engineers as well as documentation

for pre-production or production release of PCBs to manufacturing.

1990-1996: Digital Designer, Rela, Boulder, CO

. Primarily responsible for all digital design work for a third class

medical device (Intra-Aorta Balloon Pump) for a major medical client.

. Designed an Motorola 68332 based controller card that directly

communicated with an ATX 486DX processor card through an asynchronous

dual port ram interface.

. Architecture design and logic implementation target for GAL devices,

involved in the analog interface design of the data acquisition system's

A/D and D/A converters with signal conditioning circuitry. Also

responsible for logic circuit design on the power conversion DC-DC

distribution board.

. Performed signal timing and drive analysis. Involved in the design and

debug of many short and long term projects that were 68000, 8051 and

68HC11 based systems with both digital and analog circuit integration.

1986-1990: Engineering Technician, Compu-Tech Designs, Aurora, CO

. Supported i80186 base computer development effort and other projects

through schematic design/capture.

Tools used: Future-Net schematic capture software.

References upon Request

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