Manager Engineer

Roy M. Wen

******@*****.*** . c***-***-****

**** ******* *******, *** ****, CA 95139

I have routed 60 chips and help to route many in various tools. I have

closed timing with ATPG on many production tapeouts for OAK

Technology(CDROM/DVD).

Hands-on with overall ASIC methodology: device, cirucuit, library,

verilog, Synthesis, Layout, PnR and ATPG and DRC/LVS, I have MSEE degree

and 3 patents.

CAD Profile:

see> attached CAD section for details

Layout: PLA, bipolar gate array, DAC/ADC, OpAmp, PLL, Standard Cell, SRAM,

IO :

Device: Bipolar, R, C's, Supreme(Stanford Process Simulation) ;

Circuit: Spice/Hsim(FastSpice);

RTL: verilog ;

Synthesis: DC(Design Compiler, Synopsys);

Test: Tetramax(Synopsys);

Timing: PrimeTime(Static, Synopsys), HSIM, Verilog ;

PnR: GE(Gate Ensemble, Cadence), Avant! ;

DRC/LVS: USC(IBM), Dracula(Cadence), Calibre(Mentor) ;

transister level erc script development ;

utilities and softwares: perl, unix, nawk, tcl, c++ ;

Technology Profile:

0.18u, 0.13u, 90n, 45n and 32n sram fast-spice SRAM simulation, 2004-2009

0.35u and 0.18u Synthesis and DFT for asic, 2000-2003

0.65u, 0.5u, and 0.35u Standard Cell and IO library development,1995-2000

0.7u and 0.65u PnR, more than 50 gate-array chips, 1992-1995

0.7u PrimeTime QA, 1992

0.7u 1ps DLL, 1991

0.7u SRAM and library development for gate-array, 1989-1991

1.2u Standard Cell development, 1988

1.2u CMOS Analog ADC/DAC, 1985-1988

1GHz Bipolar Analog transistor design and modeling 1983-1985

2.2u NMOS PLA and EPROM, 1978-1982

Work Experiences:

01/2009-now: WIS, consultant

Developed PLL IP. Writing perl, tcl and c++ for a CAD tools.

Developing an analog asic library, op-amp, adc/dac, and filters.

Developing methodologies for Micro-chip and Quartus.

11/2004-01/2009: Virage Logic . Sr. Methodology Engineer

Supporting Fast-Spice simulators, Hsim and UltraSim, for SRAM, with

frequent multi-foundry revisions. spice model QA suite setup. Developing

transistor-level circuit ERC. QA drc/lvs for FDK's.

6/95-1/2003: Oak Technology Inc. . Library Manager & CAD Engineer

ASIC support: Synthesis(w. DFT and Timing), rtl and asynchronous io,

behavior modeling for the most profitable CDROM group. Committee member on

CDROM I/O protocol, including LVDS.

Library & Technology Manager, Responsible for more than 20 foundry

technologies, and 6 business units. Release RAMS, Standard cells, I/O's,

including PnR, Synthesis, and Verilog library views. Write and support

drc/lvs decks.

11/89-6/95: Toshiba, Circuit Design and P&R

Place and Route(PnR) using Gate Ensemble for over fifty asic's ranging

from 30K to 300K Gates. I'm familiar with clock and power structures as

well as techniques for timing closure.

High speed DLL design for joint Rambus project. SRAM design. And PrimeTime

QA.

7/88-10/89: ULSI, Digital Circuit Designer &Libraries

Standard Cell Circuit Design using HSPICE and Dracula for on HP's CMOS34

process. Mentor Apollor RTL design methodology. Library was used in

Cadence's PnR environment.

6/78-6/88: IBM, Digital/Analog Circuit Designer & Device Modeling

Circuit design for DAC/ADC and analog sub-blocks (opamps, references,

current sources, comparators, sample and holds). Device modeling including

SUPREME and DRC/LVS deck creation for all designed devices. Design

activities additionally included device / circuit design and layout for

PLA and EPLA processes.

MSEE & BSEE Brooklyn Polytech . US citizen . Mandarin

CAD Details:

Tools evolves due to new technology and increasing complexity, the

underlying principles remain the same. I have always worked in design

groups supporting CAD; these are productive experiences.

Spice: ASTAP to FastSpice

I have designed DAC/ADC with Spice like simulators(ASTAP, IBM). Later, with

20yr of spice, I was the library designer for a Intel-487

clone(successful), and Oak Technology's library manager where we supplied

the world with CDROM controllers. Library are circuit designs including

io's and standard celss. In Virage, I managed all Fast Spice simulators

used in SRAM simulations, with millions of transistors, and 10's thousands

of measurements in a single run. FastSpices, HSIM,, UltraSim, FineSim and

QuickSim, run predominantly in time domain.

DRC/LVS: USC to Calibre

These are back-end mask checkers. USC is "Universal Shape Checker", IBM,

1982, predates Cadence. I release an bipolar analog technology with it. I

worked on Calibre in Virage until 2009 on FDK's, Foundry Design Kits.

Virage supports many foundries. While I was in Oak, I worked with TSMC for

their first release of 0.6um CMOS Cadence Dracula decks, among all other

Oak's mask verification decks. I signoff lots of foundry retargeting

tapeouts, without mask changes.

Static Timer and ATPG: PrimeTime, Tetramax

This are the underlying guardian and purpose of Synchronous Logic Design

respectively. I joint IBM 30yr ago start to use this methodology. 20Yr ago

in Toshiba, I help to QA the Synopsys PrimeTime used in a Appolo CPU design

and PDP11 development. I understand Timing and ATPG very well. 10Yr ago,

Oak start to move pc asic into ATPG, I ran Tetramax(an ATPG tool) on all

0.5um and later designs.

PnR: Gate Ensemble to Advanti

As a team leader, I personally routed 50 chips in Toshiba gate array. There

are many db's to synchronize and many unique procedures, e.g. clock trees,

timing closures, to smooth out. I'm know Synopsys db well and deploys lots

of perl scripts.

Synthesis: DC(Design Compiler, Synopsys)

In Oak Technology, I coordinate the Synthesis process and take it through

Timing Driven PnR. This was the money making group, CDROM and DVD. Timing

and ATPG is also part of the deal. I coordinated the effort and debugged

any procedure that need to be fixed. That's when I switched from nawk to

perl(sed is useful one-liner in unix, but not as powerful as nawk, a

precursor of perl.)

I'v being through all phases of the ASIC development. This give me unique

advantage in debugging or developing new methodologies.

Contact this candidate