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Project Manager Engineer

San Jose, California, 95126, United States
March 29, 2011

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***** ******

**** ******* ******* . *** ****, CA 95126 . (408) ***-**** .


Electrical Engineering Professional

Results oriented and resourceful EE professional, offering extensive Project

Leadership, Solutions Development and Methodology Development / Implementation

experience within the deep-submicron Semiconductor industry. Track record of

leveraging a comprehensive understanding of leading-edge technology to innovate -

and lead cross-functional teams to deliver - technical solutions that enhance

quality, increase profits and secure an organization's long-term success.

Core Competencies

Team Leadership Training / Mentoring Patent Development Architecture


IP Evaluation / Deep Submicron Solutions Methodology

Integration Design Development Development

Professional Profile

Solutions focused - passionate about developing highly efficient solutions that

result in successful, profit generating products.

Subject matter expert and key resource who continuously investigates next-gen

technologies, novel circuits and emerging ideas.

Skilled coach and mentor - adept at communicating complex concepts / processes in a

clear, benefits driven manner.

Team builder and leader who rallies workgroups around clearly defined project goals

and actionable visions of success.

Analytical and detail focused - highly skilled at balancing the need to be process

oriented while also visualizing the "big picture."

Select Technical Skills

EDA Tools: ViewLogic, Avanti, Cascade, Mentor Graphics, Perl, Verilog, SPICE, C,

Pascal, Lisp, UNIX, Assembler, VLSI Probe Station, EMI Microscopes, OrCAD, HP VEE,

Star RCXT, AstroRail, PrimeTime, Cadence, DC, DCT, Synopsys, VirSim, SignalScan,


Design: Architecture Definition, Design, Partitioning, Implementation, Verification

and Characterization, Deep Submicron (90nm, 65nm, 45nm, 28nm) Low Power Design,

Circuit / Gate-level Design / Simulation, Custom and ASIC

Additional Skills: Timing Analysis and Closure, Clock / Power Planning, Xtalk,

Multi-VDD Domain, EM / IR-drop and Noise Analysis, DFT, IP Evaluation and

Integration, Methodology Development and Implementation, Flow Automation, Algorithm

Evaluation and Implementation, ECC, Revision Control

Professional Experience

Visa International - Foster City, CA 2010 -


Visa is a transaction payments company and global leader in its market, with over

4000 global employees and $6.9B in sales.

Project Manager - IT (2010 - present)

Responsible for planning, directing, and coordinating activities for chip card and

device products. Coordinating test tool relations with multiple test tool vendors.

Coordinating and supporting multiple testing projects including mobile activities.

Responsible for communications internally and externally regarding testing


Analyzed and benchmarked internal chip card configuration tool, identifying

performance improvements that will generate in efficiency gains of 500%. This tool

is a key step in the approval process of chip card products, i.e. cards (debit or

credit) used by consumers worldwide.

Tracked and identified bugs in internal chip card configuration tool that were

causing chip card failures and delay in schedule. Coordinating the testing and

verification of the SW fixes.

Coordinating revamping efforts of Lab equipment geared towards expanding the Lab

testing capabilities required to support the new strategic mobile products.

Altera Corp. - San Jose, CA 1996 - 2009

Altera is a semiconductor company and pioneer of programmable logic solutions, with

2700 global employees and $1.36B in sales.

Member of Technical Staff (2007 - 2009)

Responsible for leading all aspects of numerous cross-functional projects, including

complex blocks and tasks. Provided technical direction and served as a technical

resource / mentor to large group of engineers, ensuring quality and on-time project


Defined / validated multiplier / adder algorithms in DSP ASIC architecture

definition - the best in academia / industry; defined static and dynamic power

saving and improved clocking scheme. Evaluated HW/SW partitioning per DSP operation

mode and feature.

Pioneered and created new flow to characterize AC power of PnR (ASIC) blocks in a

full custom logic environment, whose tools (HSPICE/HSIM) are less expensive than the

ASIC flow tools (PT PX, ICC) and generally fully amortized.

Re-engineered differentiating ECC M-Ram feature to hit 250MHz at strategic

industrial speed bin (SS, 125C), which increased sales and market opportunities

while allowing its re-use in the hard-IP block, in addition to saving silicon area

and reducing development time.

Managed development of fuse technology for StratixIV GX in 45nm to completion while

supporting its re-use, targeting the low cost family Cyclone III. (Patent pending)

Re-engineered the fuse block to achieve 99.9999% reliability despite all possible

variations: process (corner, resistance, local variation), voltage and temperature -

a key element of all Altera chips' power up sequence.

Senior Design Engineer (2003 - 2007)

Responsible for defining, designing and verifying blocks, including guiding layout

resources and mentoring Junior Engineers.

Developed a new fuse block, integrating mixed-signal IP from foundry - a key feature

of Altera products - that provides greater flexibility in programming and increases

silicon yield >200%. Led all aspects of delivery of the fuse element technology.

(Patents 7,304,527 & 7,589,552)

Invented and designed IO configuration shift register that allows flexibility in

programming and testing FPGA's while developing systems; the key feature has been

implemented in all present and future products for its effectiveness and simplicity.

(Patents 6,842,039 & 7,287,189)

Delivery a new methodology - now a company standard procedure - for the automated

generation of complete set schematics for Stratix II family of chips, saving months

of work from schedule while minimizing errors.

Invented new fuse-based M-Ram (144Kbit) redundancy scheme that allowed scaling up

resource count 436% from StratixII to StratixIII, increasing speed and efficiency of

the chip power up sequence while reducing silicon cost 99%. (Patent pending)

Developed the differentiating M-Ram ECC feature; implemented Hsiao algorithm for

SECDED (single error correction double error detection), which reduced the area and

time impact. (Patent pending)

Advanced Design Engineer (1999 - 2003)

Responsible for designing the IC in detail, as well as supervising physical layout

to ensure conformance to schematic intent, to manage parasitics and to ensure

compliance with overall project schedule. Supported product engineers on both new

and "legacy" products.

Invented and developed an update feature, which provided users with the ability to

remotely program and reconfigure Altera chips on systems in the field, reducing

downtime and service costs associated with this task. (Patents 7,000,161 &


Developed floor plans, pintables and package matrix for Stratix I family, assuring

IO vertical migration and maximizing LVDS/DDR performance and IO counts;

simultaneously developed flip chips and wirebond packages from one database, saving

engineering cost and time and allowing SW support prior to the availability of

silicon - an innovative and company adopted standard procedure.

Enhanced JTAG instructions, providing greater flexibility to the production cycle of

systems using Altera products.

Modeled all register transfers of 20K400 and 20K600, catching and addressing errors

- avoiding $500K re-tapeout.

Automated checking of full chip logic simulations output data, minimizing errors,

saving weeks of schedule and avoiding tapeout date slip.

Design Engineer (1996 - 1999)

Responsible for learning design tools and methodologies while supporting design

projects under the guidance of Senior Engineer.

Automated characterization of the PLL block of the 10K family, saving 70% usage time

of single $300K laboratory test station.

Saved 2% die size of EPM9560 through the efficient and compact layout of the base

block, the LAB.

Minimized LVS errors 50% by writing a program to correctly associate LVS text with

its correct layer in LTL layout tool.


VLSI Engineering Certificate - University of California, Santa Cruz Extension -

Santa Clara, CA

Coursework toward Analog Design, RF IC Design, Signal Integrity, IO Protocols -

Expected March, 2011

M. Eng., Computer Engineering - University of Michigan - Ann Arbor, MI

Coursework toward a M. Eng., Electrical Engineering - University of Michigan - Ann

Arbor, MI

B.S., Electronic Systems Engineering (with Honors) - ITESM - Toluca, Mexico

Patents Issued

Integrated Circuit with Redundancy (Patent# 7,589,552) 09/2009

Reconfigurable Programmable Logic System with Configuration Recovery 03/2009

Mode (Patent# 7,512,849)

Differential Poly Fuse Sensing Circuit (Patent# 7,304,527) 12/2007

IO Configuration and Reconfiguration Trigger Through Testing Interface 02/2008

(Patent# 7,287,189)

Configuration Shift Register (Patent# 7,112,992) 09/2006

Reconfigurable Programmable Logic System with Configuration Recovery 02/2006

Mode - (Patent# 7,000,161)

Configuration Shift Register (Patent# 6,842,039) 01/2005

Configurable Memory Structures in a Programmable Logic Device (Patent# 10/2002


Patents Pending

SECDED Implementation of ECC for MRAM and 36bit ECC Wrapper Expected


Novel Chipwide Memory Repair Scheme Expected


Integrated Circuits With Fuse Programming And Sensing Circuitry Expected


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