Engineer Quality Assurance
Resume:
Parag Desai
Milpitas, CA ***35
*********@*****.***
PRODUCT TEST ENGINEER / Failure Analysis Engineer / CAD Engineer
SUMMARY
Highly accomplished Electrical Product Design Engineer with strong
knowledge of VLSI design, digital logic design, and analog/digital system
design. Considerable knowleadge in Test and Product Engineering in the
semiconductor industry. Utilize SPICE and Virtuoso for schematic editing
and simulation. Experienced in semiconductor Memory process flow and ATE
testers.
. Proven skills include knowledge of chip scale wafer level packaging
(Wraparound, MEMS). Able to remain calm and work well in high-pressure
situations, constantly seeking new challenges, a professional and detail-
oriented individual with both a strong work ethic and the desire to
exceed expectations.
. Always on schedule and under budget, able to prioritize and handle
multiple tasks while effectively achieving and exceeding project goals.
MS THESIS
Crosstalk Noise Aanalysis for Digital Integrated Circutis
This thesis describes the problem of crosstalk due to capacitive coupling
in CMOS static and dynamic circuits. The proposed algorithm identified
noise sensitivity victim nets which is based on coupling cap to total cap
ratio, victim net driving a domino CMOS logic gate and skewed beta ratio.
The pseudo code for the proposed methodology has been implemented using
Perl programming.
Once the noise sensitive victim nets are identified the next thing is to
build a noise model. The noise model consists of driver, receiver of victim
nets, aggressor, and distributed RC nets.
The PSPICE simulation used to demonstrate the effects of coupling cap (Cc)
and beta ratio on the circuit to measure the noise peak. It maintains the
coupling caps database which identifies the larger coupling caps effect on
victim nets.
EXPERIENCE
Alliacense Cupertino, CA
2006 - 5/2010
Technology Engineer 12/2007 - 5/2010
Worked closely with the engineering analyst group to analyze microprocessor
system designs. Identified the SRAM Sense Amplifier, Buffer Cell, Fast
Timing Logic, and Fast Logic Gate schematics. Simulated various SRAM Sense
Amplifier circuits for all the major memory companies.
Achieved skewed transfer function through SPICE simulation of Fast Sense
Amplifier and Logic Gate. Reverse engineered microprocessor-based systems,
including schematic \ layout analysis, hardware testing, and semiconductor
die analysis (using a scanning electron microscope).
Parag Desai
page 2
Alliacense continued
Prepared specialized reports on microprocessor-based systems which called
for an in-depth knowledge and research of microprocessor documentation,
datasheets, marketing documentation, product user manuals, product
schematics, and product designs.
Provided technical support (conferences, presentations, and response
documents), then communicated research results to senior management,
technical staffs, and external customers.
Research Presentation, CSU, LA
Wrote term paper on product manufacturing flow, the flow included from
wafer sorting to Final Quality Assurance. Term paper mainly focused on
testing methodology of various modules and test program flow. Term Paper is
not limited to test methodologies only, but also focus on effective product
cost by proposing various methods such as Test Time reduction, improve
Yield and Bin-split using core/cache recovery, optimal VID etc.
PROJECTS:
Performance Analyzer for Cache using C++
Developed a performance analyzer for Cache by various Cache Size, Block
Size and different associative, that included Block placement by using
Direct Mapped, fully Associative and Set Associative. Block replacement
using LRU (Least recently used).
To find out three different kind of misses compulsory, conflict and
capacity by using different aspect.
CMOS Cell Library Design: Schematic Capture, Layout Optimization, Cell
char., DRC & LVS
Cell library of 30 unique cells including basic gates, Multiplex, AOI,
Memory cell.
Perform floor planning, power and grounding issue and matching issue.
Distance Vector Routing Algorithm using C
The Distance vector algorithm helps nodes (routers) to send packets to
the rest of the nodes in the network using the shortest path. Each router
knows the delay to each of its neighbors.
IMMIGRATION STATUS
US Citizen
TECHNOLOGY
C/C++, UNIX, Perl, Tcl, Orcad, HSPICE,PSPICE, Cadence Design Environment,
SIMetrix Intro, Verilog, Virtuoso
L-Edit, Band-Gap Reference, VCO
EDUCATION
Master of Science, Electrical Engineering California State University,
LA, CA GPA: 3.73 Graduating 06'2011
Bachelor of Science, Electrical Engineering Gujarat University India
GPA: 3.3
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