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Project Engineer

Location:
560008, India
Posted:
March 26, 2011

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SUJAYRAJ H R

**********@**********.***

M : ***00-99755

Summary

Possess more than 6+ years of work experience in ASIC Verification & FPGA

Design.

Worked in module and SOC level verification using Specman.

Attended System verilog and OVM training.

Worked in developing new verification flows (i.e. SystemC & verilog

Environment)

Involved in complete tape out of SOC.

Worked on gate level simulation.

Industry Experience:

Curretnly working as Senior Member Technical Staff with KPIT Cummins

Infosystems Limited since Oct-2007 till date.

Worked as Senior design engineer with L&T Infotech from oct-2005 to oct-

2007

Worked as verifiation engineer with SASKEN Communication technologies from

apr-2004 to oct-2005.

Qualification:

Master of Science (VLSI-CAD), India, 2004 with 81%.

Bachelor of Engineering (Electronics and Communication), India, 2001 with

69%.

Technical Skills

HDL's Verilog, VHDL

Verification Languages Specman, C, System C, System verilog.

Simulation Tool ModelSim, VCS, NC sim.

Synthesis, P & R Tool Xilinx ISE.

Debugging Tool ChipScope Pro.

Scripting Languages Perl, Shell Scripting

BUS Protocols OCP and AMBA (AHB), P-Bus.

Other areas of exposure ASIC and FPGA Flow, Involved in verification

of OMAP3430 (ARM11 &DSP64XX) Chip, DSP processors, Clear Case Tool (CVS,

SVN).

Professional Experience

Oct 07 - till Date KPIT Cummins Infosystems Limited

Senior Member Technical Staff

Project 1 ATLAS

Description NGM consists of ARM CORTEX R4F processor which will be used

for automotive applications and is derivative of NGM.

Contribution 1. System Level Verification.

Involved in regressions, modification of environment and testcases.

Verification of ARH(Remote handler) at system level, developed sequence

libraries for system level configuration from module eVCs.

Executing verification through directed and random tests for its

functionality.

Duration November-2011 till date

Environment Specman, Cadence NC Simulator, Verilog.

Project 2 NGM(Next generation micro controller)

Description NGM consists of ARM CORTEX R4F processor which will be used

for automotive applications

Contribution 1. System Level Verification.

Verification of LIN, CRC, Remote handler and System Controller at system

level.

Developing sequence libraries for system level configuration from module

eVCs.

Executing verification through directed and random tests for its

functionality

2. LIN & RTC Module

Verification.

Verification Plan Development using eplanner.

Development of Coverage driven, self-checking, reusable verification

environment for module level verification of LIN, RTC using SPECMAN.

Developing sequence. Executing verification through directed and random

tests for its functionality.

Duration April 09 - November-2010

Environment Specman, Cadence NC Simulator, Verilog,

Project 3 OCDES(Onchip debugger for embedded system) MCU Verification

Description On chip debugger is used for debugging the CPU which has MDI

port which uses UART mode to transmit and receive data.

Contribution My responsibilities:

Verifying serial protocol.

Integrating the OCDES with the 16FX MCU and verification using System C and

verilog environment.

Duration October-08 - March 09

Environment Cadence NC Simulator, Verilog, System C.

Project 4 APIX

Description Uniquely designed to meet the bandwidth and

distance requirements of today's and future automotive connectivity

designs. Which has 1 GBit/s High-Speed Data Downlink with 62.5 MBit/s Data

Uplink, Full Duplex independent Sideband.

Contribution My responsibilities:

Verifying serial Data stream.

Building the verification environment with verilog

Duration 1 Month

Environment Cadence NC Simulator, Verilog,

Project 5 16FX MCU Verification

Description MB96F918H derivative consists of F2MC-16FX micro controller

which has 16-bit core CPU which is well suited for automotive

applications.

Contribution My responsibilities:

Running RTL simulations, Pre-Netlist and post-Netlist simulations Firing

RTL, pre-Netlist and post-Netlist regressions

Debugging test cases, make necessary modification in the test cases and

VIP.

Written new VIP for USART and test cases.

Environment Cadence NC Simulator, Verilog, System C.

Duration April 08 - September-08

Project 6 Electronic Control Unit for Power Steering

Client TKP, Hungary

Description The FPGA checks the state of the Software to be

valid or invalid. The ECU contains only one MCU (NEC Microcontroller),

hence a dedicated FPGA component is required to monitor the SW and prevent

blocking or self-steering in case of Software fault.

Contribution Fault Mode Effect Analysis (FMEA) of FPGA

design.

TOP level verification of ECU which was including various blocks like

PAS interface, UART, SPI, QAWD & IWD.

Duration 4 Months

Oct 05 - Oct 07 L&T InfoTech

Senior Design Engineer

Project 7 Excalibur Customer Premises Equipment of Wimax System

Client Navini Networks, Dallas

Description Excalibur CPE digital hardware consists of an ADSP (Analog

Devices digital signal processor), a FPGA chip and an RFIC chip. FPGA

includes signal processing and forward error correction blocks. Also it is

consists of interfaces like SPI, PPI, SPORT and RFIC and is implemented in

spartan3e (Xilinx Device).

Contribution My responsibilities included:

Design

Coding

Simulation, synthesis and board level testing.

Environment VHDL, ModelSim

Duration Sep 06 - Oct 07

Project 8 Viterbi Decoding

Client Navini Network

Description A vector of symbols is transmitted by a source travels over a

communication channel where it is corrupted by noise and interference, and

is received at a destination. The Viterbi decoder attempts to recreate the

original stream of input data at its output by using the parity symbols to

correct any errors introduced by the communication channel.

Contribution My responsibilities included design, coding and

verification of the TBM (trace back matrix) which traces back the original

data stream.

Environment VHDL, ModelSim

Duration 2- 3 Months

Project 9 Implementation of Uplink Multiple Input Multiple Output (MIMO)

Decoder for '06 4G Trial

Client Samsung, Korea.

Description Project involves in the implementation of S-MML

(Simplified - Modified Maximum Likelihood) Algorithm. In this system there

are two different multi antenna modes for '06 4G Trial uplink. One is 2X4

Multiple Input Multiple Output (MIMO), which is the collaborative spatial

multiplexing (CSM) and the other is 1X4. The MIMO operates for different

modes of Adaptive Modulation and coding (AMC) levels such as 16 Quadrature

Amplitude Modulation (16QAM) and Quadrature Phase Shift Keying (QPSK). The

system operates at 125M Hz frequency and implemented in Stratix II FPGA.

Contribution My responsibilities included design, coding and simulation

of LLR Algorithm.

Environnent ModelSim SE 6.1d, Verilog

Duration 5 Months

Apr 04 - Oct 05 Sasken Communication Technologies

Verification Engineer

Project 10 OMAP 3430

Client Texas Instrument, India

Description OMAP 3430 is a high performance multimedia application

processor which consists of ARM11 and DSP C6400 processor. Integrated on 65

nm process the device runs from 0.9v to 1.35v. The architecture is designed

to provide best in class video and graphics processing sufficient to

provide steaming video. An enhanced security feature enables e-commerce

applications. It includes support for Windows, Symbian.

SDMA: SDMA allows Data exchange between MPU subsystem, DSP subsystem,

Memory subsystem and Peripherals. DMA has three OCP interfaces composed by

one configuration port which is slave and two master ports, where one is

dedicated for read and the second is dedicated for Write. DMA also consists

of FIFO for data storage, which is useful when operating with two different

frequency domains. The data is transfer between the internal memory

(RAM/ROM) and external memories like DDR memory, SDR Memory, and integrity

of data is checked with reference to golden data.

MCBSP (Multi Channel Buffered Serial Port): Provides a full duplex direct

serial interface between the host chip and the other devices in a system.

Is an OCP Compliant interface with 5KB internal buffer for transmit and

receive Operation, Full Duplex Communication, Buffered transmission and

reception that allows a continues data stream, Capability to generate

interrupts or DMA requests on internal events.

Contribution My responsibilities included verification of SDMA,

MCBSP modules.

Environment ModelSim, VHDL/Verilog, C

Duration 8 Months

Project 11 Magnamite (MGS 3.2.0)

Client Texas Instrument, Dallas

Description Magnamite is a full chip, which uses M.G.S.3.2.0 sub chip

(which consists of DSP Processor C55x). We generated TDL's for mgs3.2.0

(the test cases which are written in C) which was converted to full chip

level and then simulated where these TDL's check for different

functionality of the DSP processors.

Contribution My responsibilities included:

TDL generation and simulation

Written script to convert TDL's from M.G.S.3.2.0 to Magnamite Level

Environment ModelSim, VHDL/Verilog, C

Duration 5 Months

Project 12 OMAP 3.5

Client Texas Instrument, India

Description OMAP system consists of ARM9, DSPC55xx, where ARM9,

DSPC55xx and OCP-I to access 256 Mbyte Multibank address space via 2 L3 OCP

external target ports these ports are also used to access single bank

memory.

Contribution My responsibilities included verification of OCP -T1, OCP-

T2 and OCP Initiator.

Environment ModelSim, VHDL/Verilog, C

Duration 10 Days

Project 13 UMA 2.4 G.L.S Simulation

Client Texas Instrument, India

Description It consists of C55x DSP Processor which is interfaced with

PORT's such as XPORT, DPORT, IPORT and MPORT and has RAM/ROM Subsystem. The

functionality of the system is verified using different test scenarios.

Contribution My responsibilities included verification of module.

Environment ModelSim, VHDL/Verilog, C

Duration 1 Month

Academic Projects

Project I Vector Floating Point Arithmetic Unit Using IEEE 754 Standard

Description The aim was to Add, Subtract, Multiply and Divide the

floating-point numbers with an extra requirement of reducing the

computation complexity. The floating-point operation was studied and it was

decided that the IEEE - 754 based architecture of the floating-point

computation will be implemented. The target was to reduce the computing and

timing requirement for each of the operation. It is to determine the

exceptions and to implement the VFPA in FPGA and the execution environment

consists of eight 80bit registers, control register, status register and

tag register.

Contribution My responsibilities included design, development,

synthesis and verification.

Environment Design Compiler, Verilog, Modelsim.

Duration 7 Months

Project II Speech Compression using RPE-LTP Algorithm and GSM 6.10

Standards

Description The aim of the project is to compress the speech Signal by

applying DSP techniques using Regular Pulse Excitation long term prediction

algorithm.

Advantage: High compression ratio of speech signal i.e.8:1

Applications: Applied in mobile communications.

Contribution My responsibilities included coding and implementing the

Algorithm.

Environment C

Duration 10 Months



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