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Digital Hardware Design. ASIC Design, Physical Design, FPGA Design

Location:
Chicago, IL
Posted:
January 14, 2015

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Resume:

JACKIEE (JUNKAI) YANG

**************@*.************.*** Personal Webpage: jackieeyang.com

847-***-**** 1915 Maple Avenue, Apt 211, Evanston, IL 60201

PROFILE

Teamwork-Oriented graduate student with extensive research and practical experience in Electrical

and Computer Engineering . Result & Performance-Focused Problem Solver with One Year Entire

Design Experience with excellent skills in FPGA, CPU Architecture in Verilog and VHDL,

Standard Cell Layout Design and Verification in VLSI & Semiconductor in Cadence Virtuoso.

Future thinker with broad visionary and strategic abilities.

EDUCATION

Northwestern University GPA: 3.76/4.0 09/2013-12/2014

Master of Science Degree in Electrical and Electronic Engineering

Teaching Assistant for EECS 213/395 – Computer System (Fall 2014)

Queen Mary University of London GPA: 3.7/4.0 09/2009-07/2013

Bachelor of Science Degree in Telecommunication with Management

A joint program with Beijing University of Posts and Telecommunications

COURSES (NORTHWESTERN U)

Advanced Digital Circuit, Computer Architecture, ASIC and FPGA Design, VLSI System Design,

VLSI System Design Project, Data Management and Information Processing, Tangible Interaction

Design and Learning, Technical Entrepreneurship Inside and Outside the Company, Independent Study

& Projects I/II

SKILLS

Programming Language:

VHDL, Verilog HDL, SystemVerilog, C, Python, Java, Perl & Tcl Scripting, SQL, MATLAB

Design Platforms:

Cadence Virtuoso XL v2010-2011, Cadence ADE XL, Cadence Virtuoso DRC\LVS\PEX Check,

Mentor Graphic ModelSim, Xilinx ISE 6.1i, Quartus II, Synopsys CosmosScope(HSpice Waveforms

Analyzer), Altera DE-2, Synopsys Design Compiler, SIMULINK, LabVIEW

Design Tools:

Adobe Lightroom, Adobe Photoshop, Adobe Illustrator, AutoCAD, Solidworks, Arduino IDE

ACADEMIC RESEARCH & PROJECTS

A 1K bit SRAM and 32 bit Kogge-Stone Adder using Cadence Virtuoso 03/2014-06/2014

Designed a 1K bit 6-Transistor SRAM using Cadence Virtuoso both on the schematic and layout

using NCSU45nm PDK technology with proper simulation.

Designed a Kogge-Stone Carry Look Ahead Adder as extra part with the SRAM to build a

prototype of a fully functioned microprocessor as the team leader.

Created the components in a very organized manner used fully standard cell design methodology.

FPGA based Tank Duel Game 01/2014-03/2014

Developed a multiplayer tank-shooting game using Altera DE-2 FPGA Development board using

Behavior and Structural VHDL.

A VGA Monitor was used to display and a PS2 Keyboard to control movement and shooting.

Design of 4 bit ALU using Cadence Virtuoso 01/2014-03/2014

Designed a 4 bit ALU using the NCSU FreePDK 45nm Technology.

The 4 Bit ALU incorporated an overflow functionality that performed functions such as AND,

XOR, OR, ADD and SUB.

The designed used Fully-Custom Design methodology to achieve the lowest area with reduced

power consumption & delay within all the groups in class.

MIPS Single Cycle Processor with 3-level Memory Hierarchy 09/2013-12/2013

Designed a memory hierarchy with 2 levels of cache incorporating the properties using

structural VHDL.

Structure as: 1KB L1-Cache with 64B linesize, direct-mapped, write-back, write allocate. 4KB

L2-Cache with 256B linesize, 8-way assoc, LRU replacement, write-through, write no-allocate

with 64-byte subblocks.

Together with a single cycle processor in VHDL that can handle the subset of the MIPS

instruction set like: arithmetic, logical, data transfer and conditional branch operations

WORK EXPERIENCES

Electrical Circuit Logic Engineer FAW-Volkswagen 06/2014-09/2014

Assisted the Senior Engineers in the Electronic Device Planning Department to use the DL24

(Datenlogistik24) and CANoe system to test and diagnose the logic and performance of the Anti -

Theft Alarm System for Engine.

Assisted in the verification and design on BCM (Body Control Module) and Laser-LED Car

Headlight System Circuits functions throughout the CanOE tool on the BJ40 test vehicles .

Presales Technical Consultant Engineer Hewlett-Packard (China) 06/2012-08/2012

Practiced on the HP BladeSystem-Proliant (iLo), installed the RED HAT OS to 30+ HP BL495c

servers

Participated in the maintenance and monitoring for the HP BL480c servers in HP/EYP China Data

Center

Studied and Made Presentation for the general procedure of CDSM Sales Process Pipeline

OTHER ACTIVITIES AND INTERESTS

Assistant Photographer for Beijing Olympic Games Aug 2008, Beijing, China

Mar 2010 – July 2012

Chairman of Photography Club of BUPT

AWARDS

Honored the Gold Medal of Integrated Product Design Group of 2011 China -ASEAN International

Youth Innovation Contest via “A Movable Environmental Detection and Regulating System Based On

Smart Home Technology” Dec 2011

OTHERS (Working Authorization)

Working Authorization in United States in OPT with Valid EAD (Employment Authorization Document)

Card from December, 2014



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