Design Engineer
Resume:
Amitkumar Mane
Chatsworth, CA 91311
abhn8n@r.postjobfree.com
Objective: To obtain a challenging position of Lead Hardware/Firmware Design
E ngineer in the area of FPGA, DSP processor and M icrocontroller based digital system
design.
Experience
Company : I nnovative I n tegration I nc. May 2003 till
d ate
T itle : Senior H a rdwa re Design Engineer
Duties
o Design high speed analog/digital mezzanine boards for DSP and Data
Acquisition using ADC,FPGA,DAC,DDR Memory and DSP Processors
o Project Management: develop schedules, cost estimation, acceptance test
p rocedures, manage Jr. Design Engineers
o RTL coding of DSP IP cores (FFT,FIR Fil ters,DDC,OFDM modulators,
demodulators), implementation and verification using Xilinx System
Generator, ISE and Matlab/Simulink
o H igh speed ADC and DAC in terface design using VHDL for Xilinx FPGAs
o QDR SRAM,DDR, DDR2 SDRAM, UART, SPI interface logic using VHDL for
X ilinx FPGAs
o H igh speed SerDes (RocketIO) in terface design using Xilinx Vi rtex2Pro,
V ir tex5 and Vi r tex6 FPGAs
o Implementation of Digital Down Converter (DDC) for GSM applications on
V ir tex2Pro,Vir tex5, Vir tex6, Spartan 3A DSP FPGAs and TI GC5016 chip
o Power supply design for FPGAs DSPs and ADC/DACs on various boards
o Development of Matlab Board Support Packages for various boards
o Design of various adapters for XMC/PMC form factor boards using PADS
PowerPCB
o In terface and collaborate with software engineers and customers
o Testing and t roubleshooting using logic analyzers, spectrum analyzers, signal
generators and Xilinx Chipscope
Amitkumar Mane
9961 Lurline Ave #315
Chatsworth, CA 91311
abhn8n@r.postjobfree.com
O utstanding Ha rdwa re Designs
o Quadia
Four TI DSPs( TMS320C6416), Two Xilinx FPGAs(XC2vp40) on a
CompactPCI form factor board
o X5-400M
Two 400Mhz ADC(14 Bits), Two 500MHz DAC (16 bits), Xilinx Vi r tex5
F PGA on XMC form factor board
o X5-RX
Four 200MHZ ADC(16 Bits), Xilinx Vi r tex5 FPGA, DDR2 Memory on
X MC form factor board
o X6-100M
Two 1 GSPS ADCs ( 12 bits), Two 1 GSPS DACs (16 bits), LPDDR
Memory, one Xilinx Vir tex6 FPGA on XMC form factor board
o P MC-UWB
Two LTC2242-12 ADC(250MHz) and one Xilinx Vir tex2Pro FPGA on
P MC form factor board
o P MC-D R
Four LTC 2255 14-bit, 125 M Hz ADCs, One Xilinx FPGA, DDR
memory on PMC form factor board
O utstanding Custom P rojects
o 3GPP LTE PHY layer implementation on Vir tex5, Vi r tex6 FPGA
o 3GPP LTE Downlink EnodeB waveform generator on Vi r tex5, Vir tex6 FPGA
o 40 Channel DDC on Vi r tex2Pro FPGA for Commnucation et Systems, France
o 400MHz Wideband Receiver for EHS, Germany
o 1,4,8 Channel DDC IP core on Vir tex5 FPGA for Onera, France and US Navy
o Custom fil ter, FFT design for Fugro L td, Australia
o 64 board Synchronous DDC receiver for DSPCON,USA
o PID controller on FPGA for Nanonics, Israel
Amitkumar Mane
9961 Lurline Ave #315
Chatsworth, CA 91311
abhn8n@r.postjobfree.com
o Falcon Eye RADAR hardware development for Mustang Technologies, USA
Company : Ajay Electronic P roducts
J une1999/July2001
T itle : E mbedded System Design Engineer
Duties
o Circuit Design and verification of products to measure various process
parameters such as f low, temperature
o Development of PLC drivers, LED display drivers, RS232-485 converter
o fi rmware development using C,C++ for 8051 microcontrollers
o Development of custom applications using SCADA systems to measure and
monitor various process parameters
Company : Texas Tech University J anua ry 2002/Dec 2002
T itle : Teaching Assistant
Duties
o Reviewing and Teaching course material
o Preparing and conducting Lab Experiments
Technical Skills
P rogramming Languages :
M atlab, VHDL, Verilog, C, C++, In tel MCS51 assembly language
Software Tools:
Amitkumar Mane
9961 Lurline Ave #315
Chatsworth, CA 91311
abhn8n@r.postjobfree.com
Xilinx ISE foundation, Chipscope, Xilinx System Generator, ModelSim,
M atlab/Simulink,PADS PowerPCB, Orcad Schematic Capture CIS, Microsoft Visual
S tudio 2005, TI Code Composer Studio, Pspice
Bus Standards:
PCI, CompactPCI, PCIexpress, PMC,XMC
E ducation
M.S. in Electr ical Engineering GPA 4.0/4.0
Texas Tech University, Lubbock Tx 2003
Area of Emphasis : D igital System Design
Graduate P rojects
o 8 bit Simple RISC Processor Design in verilog using Xilinx ISE 5.1 and
Spartan I I-E
o 8085 Microprocessor design in VHDL using Xilinx ISE 5.1 and
XC4000E FPGAs
o Modeling SIO MOS device using Pspice
o DTMF encoder/deocde using TMS320C6711
o Caller ID implementation using Matlab/Simulink
Post Graduate Diploma in VLS I Design 2000
Bitmapper I n tegration Technologies, Pune, I ndia
Bachelor of Engineering ( Inst rumentation)
Distinction
Shivaji University 1999
Special Achievements
o Merit Scholarship from Electrical Engineering Department, Texas Tech University
o National Scholarship from Maharashtra State Government at high school level
o General scholarship from Maharashtra State Government at primary school
Amitkumar Mane
9961 Lurline Ave #315
Chatsworth, CA 91311
abhn8n@r.postjobfree.com
Papers
COTS digita l r adio receiver system is good to go, w ww.dsp-fpga.com, 2006
References:
Available upon request.
Contact this candidate