Design Engineer

GURUNATH DOLLIN

***** ******* ** *** *, Northridge, CA-91325 (818) 527-

3115

**************@*****.***

OBJECTIVE

Seeking a design/testing engineering position utilizing education/technical

experience and thereby contribute to the firm productively and gain

invaluable work experience.

SUMMARY

. Over 2years hands on experience with VHDL and Verilog languages, System

on programmable chip (SOC), Digital Circuit Design. Xilinx: ISE tool;

Altera: Quartus, NIOS II, SOPC builder; Cadence.

. Hands-on experience with Altera Cyclone II Processor, Xilinx Spartan.

Good experience working with Hardware description language, digital

circuit design, standard layout chip design, hardware simulation &

debugging.

. Excellent C/C++ programming skills wrote drivers for custom built

hardware and controlled various operations in System on Chip.

TECHNICAL SKILLS

. EDA/CAD tools from Xilinx, Altera and Cadence ( Xilinx ISE, Modelsim,

Xpower, Coregen, Quartus, Nios II IDE, SOPC Builder, IC Compiler and

Design Compiler.

. HDL: VHDL, Verilog ( Assembly Language: 8085/8086 ( Familiar with

debugging tools: Logic Analyzer, Signal Probe.

. Programming Language: C, C++. ( Scripting Language: Perl.

. Microcontroller: Atmel(8051, AVR32), Microchip(pic16, pic32),

Motorola(68hc12), ARM(Familiar Cortex M3).

. Tools: Matlab, Pspice ( IDE tools: Code Warrior, Raid, and AVR Studio.

. OS environment: Macintosh OS X, UNIX (Solaris), Windows XP/Vista/7.

. Applications: Microsoft word, excel, power point; pdf.

EDUCATION & RELEVANT COURSEWORK

MS, Electrical Engineering, California State University Northridge (CSUN)

GPA: 3.75/4.00

BE, Electronics and Communication Engineering, INDIA. July 2009

GPA: 3.9/4.00

FPGA/ASIC Design using VHDL System on Chip Design

(pSOC) Diagnosis/Reliable Design of Digital systems

Digital System Design using VHDL Microprocessor &

Microcontroller Digital Logic Design

Advanced Computer Architecture Advanced switching

theory Digital Sys Design using Prog logic (CPLDs)

ACADEMIC PROJECTS

Flash Memory-based .wav File Music Player on Altera Cyclone II FPGA

. Designed a Music player on Altera DE2 Development board. Integrated NIOS

II soft-core processor, custom FIFO, flash memory interface, shift

register and other I/O interfaces in multiple clock domains.

. Software was coded and debugged in C using NIOS IDE environment to

control operations of the processor.

. A state machine is designed in VHDL to configure Wolfson WM8731 Audio

Codec on DE2 board to the required specifications.

. Achieved design specifications, tested and verified timing in real-time

using Logic analyzer. Design correctness is verified from digital logic

simulation with RTL and gate-level models.

Rotating LED Message Display System Using PIC16.

. Software was coded and debugged in C using CCS environment.

. Here only 8 LEDs are used to display any complete message.

. The concept used here is Perception of Vision.

Sony and Panasonic Remote controller sequence detector

. Designed a complex programmable synchronous state machine hardware in

VDHL which detects Sony remote by default and when reprogrammed detects

Panasonic remote is used as a component in NIOS system.

. The NIOS system containing state machine, timer, memory element, NIOS II

soft core processor is loaded to Altera DE2 board through USB Blaster,

and this system is connected to IR detector in the DE2 board, where

remote sequence is captured.

And many more Projects.

WORK EXPERIENCE

. Jr Embedded Engineer: Worked as a Volunteer on a project in Brazen Tek

Company, California, US. (Jun-Aug 2010).

. Lab Technician: Working as Electrical Engineering Lab Technician. (Aug

2010)

. Teaching Assistant: Tutored digital hardware testing, low power

technique, Routing, Placement, Clock tree synthesis concept for the

class(Gave an Introduction to Cadence Design Compiler and IC Complier

tools( Worked as a grader for Home works and exam papers.

References

available.

Contact this candidate