Engineer Design

SAINATH NIMMAGADDA

*** *. ********* ***. 512-***-****

Chandler, AZ 85226 ********@*****.***

ABOUT ME

Senior-level High-speed Signal Integrity & Power Delivery Engineer with

a PhD in Computational Electromagnetics/ Microelectronics from the

University of Illinois, Chicago and 12 + years of IC-Package-PCB co-design

experience in Semiconductor & Electronic Design Automation(EDA) companies.

Received several corporate recognition awards and customer appreciation

awards for New Product Introductions and Modeling Algorithm Improvements.

Self-motivated and results-oriented. Hands-on technical expertise. Solid

individual contributor and team player. Take ownership of projects, concept

through completion, and deliver results consistently in a timely manner.

Proven ability to successfully carry out multiple projects concurrently

with ease.

Proactive and take initiative. Ability to provide technical inputs to

management to make trade-off decisions. Have effective people skills to

successfully interface with management, technical teams, customers and

vendors. Strategic negotiator, hard-working and dependable.

Team Lead and Project Management experience. Trained in Six Sigma and

Lean. US citizen.

KEY STRENGTH

Technical leadership and talent for coordinating with cross-functional

product development teams and CAD tool vendors to deliver innovative IC-

Package-PCB co-design solutions that enable cost-effective solutions and

first-pass success.

TARGET POSITION

. Work on cutting-edge, exciting technology product

. World-class work environment

. Room for technical and personal growth

. Top pay and comprehensive benefits package

CORE COMPETENCIES

Signal and Power High-Speed Digital IC-Package-PCB Co-design

Integrity Design

IC Package Modeling CMOS Device Modeling System-Level HSPICE Sims

EM Field Solvers High-Speed Lab Testing SoC Design Guidelines

TECHNICAL QUALIFICATIONS

PhDEE (Computational Electromagnetics/ Microelectronics), University of

Illinois, Chicago.USA.

MSEE (Microwave Engineering & RF Systems), Indian Institute of Technology,

Kharagpur. India.

BSEE (Electronics & Comm. Systems), Jawaharlal Nehru Technological

University, Hyderabad. India.

PROFESSIONAL EXPERIENCE

Signal Integrity & Power Delivery Engineer (Contract), INTEL, Chandler, AZ,

3/11 - 5/11.

Signal Integrity Engineer (Contract), MICROSEMI, Phoenix, AZ, 10/10 -

12/10.

. Signal integrity & power delivery analysis of high-speed interfaces

such as DDR3.

. Package model extraction, simulation and analysis of DDR, PLL, DLL and

CLK power rails

. Flip-chip Package S-parameter model extraction using Sigrity tool

PowerSI

. HSPICE equivalent circuit model extraction using Sigrity tool

Broadband Spice(BBS)

. Time-domain & Frequency-domain simulations of IC-Package-PCB co-design

using HSPICE.

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Sr. Staff Signal Integrity Engineer, FREESCALE SEMICONDUCTOR, Austin, TX,

2005 - 10.

. Lead the package modeling team and developed IC package simulation

capabilities to support major customer groups: Consumer Electronics,

Networking, and Automotive.

. Performed electrical simulations & modeling of packages: RLC, IBIS,

Spice and S-parameter models

. Developed modeling methodologies for Package-on-package, flip-chip,

wire-bond and lead-frame (QFP, QFN) packages

. Performed signal and power integrity analysis to verify package

electrical integrity

. Worked with product groups and package designers on new products

development

. Hired junior SI Engineers and trained them in productive tool usage

for package simulations.

. Evaluated tools, arranged for NDA, procured tools and managed

licensing/maintenance issues

. Extended simulation capabilities with latest 64-bit hardware and

variety of software tools

. Tools used: Sigrity: XtractIM, Speed2000, PowerSI; PowerDC; Apache

PakSi-E; Ansys: Icemax; Ansoft: Turbo Package Analyzer, Q3D, SI Wave;

Cadence: Allegro, APSI 620

. Performed time-domain and frequency-domain simulations.

. Developed and documented simulation methodologies, package design

rules and simulation inputs and outputs specifications.

Sr. Member of Consulting Staff, CADENCE, San Jose, CA, 2002 - 04

. Lead the consulting efforts of power grid analysis tool VoltageStorm

. Performed gate & transistor level power/ground net analysis.

. Performed IR drop, current density & electromigration risk analysis

. Used Fire & Ice QX for RC extraction and VoltageStorm for analysis

. Coordinated with AE and QA groups. Solved customer issues.

Sr. Signal Integrity Engineer, COGNIGINE, Fremont, CA, 2001 - 02

. Coordinated with IP providers of Line Framer and Switch Fabric and

understood the system-level signal integrity sign-off issues of a

Network Processor (10 Gb/s).

. Coordinated with cross-functional teams on Chip, PCB and package

design integrity.

. Simulated LVDS, DDR, PCI, SDRAM, SPI-4.2 environment & timing analysis

using Hspice.

. Evaluated and recommended Cadence VoltageStorm for IR drop and

Electromigration risk analysis.

Sr. Signal Integrity Engineer, LSI LOGIC, San Jose, CA, 1999 - 2001

. Verified system-level signal integrity of high-speed tranceivers (2.5

Gb/s)

. Tested HyperPHY tranceiver performance in terms of bit error rate

(BER), setup/hold times, jitter and eye diagrams. Used oscilloscopes,

spectrum analyzers, TDR, IConnect, VNA and BERT.

. Performed Hspice simulations to determine the transceiver performance

including crosstalk and simultaneous switching noise (SSN)

. Designed test cases and evaluated 3 signal integrity tools (Agilent:

ADS/MDS, CadMOS: SeismIC, SnakeTech: LayIN)

. Developed and documented design rules for mixed-signal design

improvements.

. Simulated and modeled flip-chip and wire-bond packages using HFSS and

TPA tools.

Sr. On-Chip Device Modeling Engineer,

SYNOPSYS, San Jose, CA, 1998 - 99

. Performed on-chip DC, CV and s-parameter measurements for CMOS device

parameter extraction.

. Developed Level-28, BSIM3, and IBIS device models.

. Used Cascade Summit prober, Semiconductor Parameter analyzer, LCR

meter

. Performed interconnect modeling (Raphael, Star-RC and HSPICE)

simulations.

. Performed process modeling (Davinci) & device modeling (Medici, Device

Model Builder, META)

PUBLICATIONS, AWARDS & REFERENCES Will be provided upon request

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