Engineer Design

**** **** ****

Pflugerville, Texas *****

Phone: 512-***-****

Email: **********@*****.***

Andy Huynh

Objective Seeking a full time position with an emphasis in

Physical Design/Integration position.

Summary Physical Design/Integration Engineer with 2+ years

experience in macros floor-plan, place and route,

timing closure, physical verification checking DRC/LVS

in PowerPC microprocessor 32nm, 22nm technologies.

Flexible working style and ability to learn new skills

and material quickly.

Enjoy working independently or as a high contributing

member of a team.

Technical Working knowledge of Perl, Assembly, C coding, Verilog

Qualification Frequently used tools: Cadence Virtuoso, Oscilloscope,

and Skills and Logic Analyzer.

Familiar with standard PC system architectures: SPI,

PCI/PCI-express, DDR

Professional IBM, Austin, Texas 08/08-Present

Experience Physical Design/ Integration Engineer

Work on physical design process from RTL to tape-out,

including synthesis, floor-planning, place and route,

timing closure and physical verification (LVS/DRC)

Responsible for place/route of complex high performance

PowerPC processors in advanced process technologies

32nm, 22nm.

Define the floor-plan, including pin placement, power

busing, placement of blocks and macros

Perform net-list to physical design including

place-and-route, extraction, timing closure and

physical design verification (LVS/DRC).

Validate a series of checks which verify that all

design constraints are met.

IBM, Austin, Texas

02/04-08/08

PowerPC Validation Engineer

Responsible for bring-up and debug of tester platforms,

execution of bring-up and validation test plan, and

development of verification strategy for high speed

IOs.

Responsible for design validation of PowerPC

microprocessor to the hardware specifications level

debug.

Tested, debugged and simulated PowerPC embedded

systems.

Performed functional testing and analysis of Linux

systems under development.

Wrote C program to control voltage setting on

evaluation platforms.

Converted the firmware level memory initialization to

high level serial peripheral interface (SPI) to access

to memory interface control for read and write to

memory registers by using C programming.

Used Perl and Bash scripts to automate regression

tests.

Performed system-level debug and resolve issues on

systems failing in Test, Development, or Mfg, as

needed.

IBM, Austin, Texas 09/03-11/03

Hardware System Test Engineer

Performed functional testing and analysis of UNIX

server systems under development.

Integrated processors, memory cards, I/O cards, and

other components into functional processor subsystem

for IBM p-series servers.

Powered-on and validated design of key chips, cards,

and other HW components, and bring up integrated

hardware for IH Mid-Range Server, to meet key

mile-stones such as chip RITs, card gerbers.

Resolved issues and opened defects via CMVC.

Supported for firmware programmers, system test

engineers and Linux product test engineers.

Loaded AIX, firmware, and operate diagnostics tools

such as HTX and test equipment.

Motorola, Austin Texas

07/00-10/02

Verification Engineer

Verified logic block through verilog based verification

environment for PowerPC embedded microprocessor.

Modified behavioral in C, which can be used to

initialize, configure and randomize facility values at

a specific cycle in the simulation.

Ran test cases to perform embedded verification using

assembly, C that developed and provided feedback to IC

designers regarding improvements to the design from a

functionality perspective.

Created test cases using RPTG/Raptor test generators.

Wrote assembly code to develop specific test cases.

IBM, ASIC Design Center, Austin Texas

08/99-05/00

ASIC System Level Timing Co-op Engineer

Applied interconnect modeling, static timing analysis

tools to specify, verified critical net timing at the

board and system level.

Applied EDA tools and procedures to model and analyze

critical net timing and signal integrity for systems

under development

Generated system level timing models for IBM ASIC

RS/6000 workstations.

IBM, System Integration I Division, Austin, Texas

08/97-08/99

Bring-up/Hardware System Test Co-op Engineer

Performed functional test of development products.

Simulated customer problems, determine the problem area

using scopes, logic analyzer and other troubleshooting

tools.

Measured timing and signal quality.

Troubleshot to component level using schematic and

oscilloscope.

Installed AIX, firmware, and operate diagnostics tools

such as HTX and test equipment.

Debugged logic fails, interfacing with system and logic

designer.

Education The University of Texas at Austin

Bachelor of Science in Electrical Engineering: May 2000

Related Courses

VLSI Design Computer Architecture

C/C++ Programming

Digital System Design Logic Design (VHDL)

Assembly Language

References Available upon request

Employability status: US Citizen

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