Electrical Engineer Design

OBJECTIVE:

To obtain a fulltime position as an Electrical engineer that will allow me

to utilize and further enhance my technical ability in Analog, Digital,

Mixed-signal, CMOS RF IC circuit design, layout and ASIC/FPGA

Design/Verification and application.

EDUCATION:

Master of Science Candidate, MAY Bachelors of Engineering, July 2007

2011 Electronics and Telecommunication

Electrical Computer Engineering Engineering

California State University, Pune University, India

Northridge (CSUN)

MAJOR COURSES:

FPGA/ASIC Design Verilog HDL

Digital Signal Processing Diagnosis and Reliable Design of

Computer Arithmetic Design Digital System

Design Auto VHDL ASIC Development

VLSI Embedded System

Microcontroller & Microprocessor Microwave communication

PROFESSIONAL EXPERIENCE:

Designed Multicycle CPU using VHDL

09/2008-11/2008

. Defined and design Multicycle CPU in VHDL using Xilinx software

. Designed different parts of CPU individually & finally wired them

together in main programmed

. Analyzed each part behavior & whole design using Modelsim while

designing

Electronics & Telecommunication: Biometrics (Identification using

Fingerprint & Voice Recognition):

01/2007-06/2007

. Designed Fingerprint Identification system using MATLAB

. Build Voice Recognition System using FSM2007

Design synthesizable asynchronous FIFO using 90nm Library. 10/2009-

11/2009

. Tasks include RTL design of FIFO

. Understanding the concept of Cross Clock Domain and implement it

. Simulate FIFO using Cadence for Timing Analysis

. Use synopsis's DC Compile for Top-down and bottom-up method using 90nm

library

DESIGN OF CONTROLLER FOR DATA ACQUISITION SYSTEM USING LABVIEW AND NI-PCIe

6537

01/2010-06/2010

. Tasks include Design and Developed DAQ Controller

. Hardware used: National Instrument Digital Input/output Board PCIe

6537

. Software Used: Lab VIEW, Orcad for design Layout

. Physical sensors used: 4*4 Photodiode array (wavelength ?=0.9 m)

University Student Union

07/2010 - Present

California State University, Northridge

Clerical Assistant

. Assisted and coordinated with the department to conduct duty related

to office such as Budget, Opening P.O. and Budget Modification.

University Corporation 08/2009-

05/2010

California State University, Northridge

Student Assistant

. Duties Include, Marketing, Retail, Customer Services

Design RISC CPU using Verilog HDL in Cadence 04/2009-05/2009

. Design Memory, Instruction Register, ALU, Controller, Counter, Clock

Generator, Register in Cadence

. Compile each module separately

. Wired each module in top design and compile it with cadence

CERTIFICATION/SKILLS:

. Familiar with Hardware Designing Tools.

. Participated in seminar on "Mobile Computing and Wireless Networking"

. Attended expert lecture series on "Recent Advance in Electronics and

Telecommunication Technology"

. Worked on 90nm library

. Certified in C & JAVA (BASIC) language.

COMPUTER SKILLS:

HDL Language Software Operating Systems

Verilog HDL, VHDL Mat Lab, Cadence, Windows, Mac, Linux, Sun

Perl, TCL Xilinx, Altera, Synopsis

Lab VIEW

Language

C, C++,Java

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