Design Project

VISHNU PRASATH .S (:

**************@*****.***

(: 919*********

Domain Expertise (Baseband) ~ FPGA Design & Development Life Cycle ~ Client

Interaction

Relationship Management ~ Team Management

"Excels in resolving technical issues, delivering outstanding Performance

Excellence and achieving assigned targets"

Seeking a challenging position in telecommunication and Semiconductor

Company that offers a creative and challenging environment for

technological innovation, excellence and advancement.

> Total 6 years of experience

> HCL Technologies as Technical lead - June 2009 to till date

> HCL Technologies as Lead Engineer -June 2008 to May 2009

> Data patterns as Hardware Design Engineer - August 2005 to May 2008

TECHNICAL SKILLSET

> Hardware Description Language - Verilog, VHDL

> Programming Language

- C++, TCL, VBA

> FPGA synthesis - Leonardo

Spectrum, Synplify

> FPGA Implementation - Xilinx ISE, Altera

Quartus

> EDA Tools - Modelsim,

Xilinx Simulator

> FPGA Logic Analyzer - Xilinx Chip scope,

Altera Signal TAP

> Schematic Editor - HDL Author, Xilinx

Schematic Editor

> DSP Simulation - MATLAB Simulink,

System Generator

> Timing Analyzer (STA) - Xilinx Timing Analyzer

> Technology - LTE,

GSM, RADAR, CDMA

> Protocols -

CPRI, PCI, VME, SPI, I2C, ARINC 429, FVTP, UART

Educational Qualification

> Master of Technology (M.Tech), July. 2005,

Major: VLSI Design

CGPA: 8.7

University Rank Holder

> Bachelor of Engineering, July. 2003,

Major: Electrical and Electronic Engineering

Overall Percentage: 77%

Career Highlights

. Pivotal in enhancing the standard practice in FPGA design life cycle

through the following initiatives:

. Created reusable IPs in FPGA design

. Implemented the pipelining concept in RTL design process and Firmware

design process.

. Excellent Debugging through Spectrum analyzer, Chip scope and Signal

tap

. Instrumental in optimizing the efficiency of the FPGA design life cycle

time by 20%.

Career Overview

. Involved in requirement study and analysis, preparation and review of

Documents including Register Details, RTL & Schematic design, and

simulation for functional & timing closure.

. Responsible for coordinating with RF Design Team, Digital Design Team

and Software Design Team.

. Client Interaction for ensuring requirements, accountable for proto

Testing & qualification.

. Prepared & reviewed test cases, generated test report and test log.

projects

Project # 1: CDMA/LTE REMOTE RADIO HEAD

Company NAME: - HCL Technologies

Client: - powerwave technologies

Team SIZE: - 2

Tools: - Xilinx 12.2i, Modelsim 6.0SE, MATLAB 7.0, SIMULINK

LANGUAGE: - VHDL

System hardware: - Virtex-5 35T

Wireless base station transceiver front-end signal processing is often

performed using digital techniques. Provided DSP algorithms to meet base

station specifications using analog to digital conversion rates of LTE/CDMA

2000. Demodulated 12 CDMA/4 LTE carriers and implemented decimation filters

using XILINX IP CORE. Basically this product is delivered in two phases -

with LTE designed and developed first followed by CDMA.

Roles & Responsibilities:

> Architecture Design of DDC filters for LTE and CDMA.

> RTL Coding and Integration of DDC Filters

> Implemented Gain Ranging Loop (GRL) to bring the ADC input to the

acceptable level

> Synthesis and timing analysis to run the FPGA at 368MHz.

> Board validation of the DDC filters

Project # 2: A5/1 stream Ciphering algorithm

Company NAME: - HCL Technologies

Client: - powerwave technologies

Team SIZE: - 1

Tools: - Xilinx 12.2i, Modelsim 6.0SE, MATLAB 7.0, SIMULINK

LANGUAGE: - VHDL

A5/1 is a stream cipher used to provide over-the-air communication

privacy in the GSM cellular telephone standard. The algorithm was

implemented to upgrade the module for security purpose. The algorithm has

two FSMs, one generates the cipher key and the other generates the cipher

stream data at the chip rate.

Roles & Responsibilities:

> Architecture design of A5/1 Algorithm

> Designing and coding of ciphering and de-ciphering

algorithm.

> Involved in functionality simulation of module.

> Developed automated tool integration in VBA platform for

module level synthesis.

Achievements:

The development of automated tool integration reduces the time of

manual intervention of compilation in HDL author and synthesis enclosure in

Quartus/Xilinx. As the tool runs in command prompt mode, the execution was

found to be much faster than the GUI mode.

Project # 3: wireless Repeater

Company NAME: - HCL Technologies

Client: - powerwave technologies

Team SIZE: - 4

Tools: - quartus 8.0, Modelsim 6.0SE, MATLAB 7.0, SIMULINK

LANGUAGE: - VHDL

System hardware: - altera - stratix III

Wireless repeater is a bi-directional digital amplifier and can be

configured for maximum of 5 sub-bands. It down converts 5 channels to

intermediate data, adjust the gain, up convert and send it to DAC.

Roles & Responsibilities:

> Architecture design of Half band filters.

> Coding of Channel filter and HALF BAND Decimation and interpolation.

> Synthesis, board testing, and debugging.

Achievements:

Received appreciation from the client for solving the issue in a span

of one day.

Project # 4: single carrier base station

Company NAME: - HCL Technologies

Client: - powerwave technologies

Team SIZE: - 4

Tools: - quartus 8.0, Modelsim 6.0SE, MATLAB 7.0, SIMULINK

LANGUAGE: - VHDL

System hardware: - altera - stratix III

This is a GSM (2G) base station with GMSK modulation scheme. This

module supports both digital down conversion and digital up conversion. DDC

filters down convert the 28 carrier GMSK data from 104Msps to 546kbps. The

DUC filters up convert 270.833ksps to 155.99 Msps.

Roles & Responsibilities:

> Architecture design of DUC.

> Coding of Channel filter and HALF BAND Decimation and interpolation.

> RTL integration for DUC.

> Implemented Gain Ranging Loop (GRL) to bring the ADC input to the

acceptable level.

> Involved in synthesis, board validation.

Project # 5: DESIGN AND FPGA IMPLEMENTATION OF BPsK DEMODULATION

Company NAME: - DATAPATTERNS India pvt limited

Client: - isRO satellite communication

Team SIZE: - 2

Tools: - Xilinx 8.2.03i, Modelsim 6.0SE, MATLAB 7.0, SIMULINK

LANGUAGE: - VHDL

System hardware: - virtex -4

The onboard Baseband system comprises a Costas loop BPSK demodulator,

In-phase /Mid-phase bit synchronizer with Integrate and dump circuit, and

corresponding lock detector circuits. This module has a line of filters

which does digital down conversion and demodulates the bits. This module

does frequency correction and phase correction.

Roles & Responsibilities:

> Architecture design of costas loop

> Implementation of algorithm to RTL conversion

> Involved in synthesis, board testing, and debugging

> Implemented Gain Ranging Loop (GRL) to bring the ADC input to the

acceptable level

Project # 6: tRACKING RADAR

Company NAME: - DATAPATTERNS India pvt limited

Client: - THumba Equatorial Rocket Launch Station

Team SIZE: - 2

Tools: - Xilinx 8.2.03i, Modelsim 6.0SE, MATLAB 7.0, SIMULINK

LANGUAGE: - VHDL

System hardware: - virtex - II, spartan -II

This system consists of two modules

1) Digital IF Processor

2) IO module

Digital IF Processor receives raw data signal (33 Hz AMPLITUDE & PULSE

modulated) from radar receiver system and converts analogue signal into

digital signal through a high speed ADC (DDR). The Filters implemented is

to extract the amplitude modulated 33Hz component from the baseband. By the

extraction of 33Hz component, azimuth and elevation errors are calculated

which is used to give the direction of the line of sight of the target to

the angle tracking subsystem.

IO is a standard VME product. The VME configuration A16-D16,

A24-D16 and A32 D32 mode are implemented in Spartan-2. A32 D32 BLT (Block

Level transfer) had been implemented for achieving 50MHz rate.

Roles & Responsibilities:

> Implementation of VME configuration

> Architecture Design of DDC filters.

> RTL Coding and Integration of DDC Filters

> Implemented Gain Ranging Loop (GRL) to bring the ADC input to the

acceptable level

> Synthesis and timing analysis to run the FPGA at 150MHz.

> Board validation of the DDC filters.

> Support to client Integration testing at customer place.

Achievements:

RADAR system successfully tracked CARTOSAT-2A launched on 28 April'2008

from Tumba Equatorial Rocket Launch Station, Tirunvananthapuram India.

Project # 7: PS/2 KEYBOARD INTERFACE MODULE

Company NAME: - DATAPATTERNS India pvt limited

Client: - Aeronautical Development Agency (ADA)

Team SIZE: - 1

Tools: - Xilinx 8.2.03i, Modelsim 6.0SE

LANGUAGE: - VHDL

System hardware: - spartan -II

This module is interface between keyboard and DSP processor. It

decodes/encodes the data and clock from/to the keyboard/processor.

Roles & Responsibilities:

> Implemented FSM for decoding and encoding.

> Board testing.

Project # 8: DELTA SIGMA DAC INTERFACE MODULE

Company NAME: - DATAPATTERNS India pvt limited

Client: - RCI DRDO Hyderabad

Team SIZE: - 1

Tools: - Xilinx 8.2.03i, Modelsim 6.0SE, MATLAB 7.0, SIMULINK

LANGUAGE: - VHDL

This module takes I and Q sample from the DDC filter chain and

converts it into DAC input readable format.

Roles & Responsibilities:

> Prepared specifications according to the requirements.

> Implementation of DAC interface module.

> Analyzed existing top module and integration of DAC

interface module.

> Board validation of DAC interface module.

Awards and Achievement

> Outstanding performer award for the year 2010, 2009

> Got a number of appreciation mails from the

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