Engineer Project

DHIRAJ VANIK

Artesia, CA - *****

Email: ******.*****@*****.***

Phone # 818-***-****

Open to transfer/relocate

OBJECTIVE:

To obtain the position of a Electrical (Analog or Digital) Design and test

engineer in a reputable organization that will offer me an opportunity to

utilize my professional experience towards professional growth and

development

EDUCATION:

Master's in Electrical Engineering (2007 - 2010)

California State University, Northridge

GPA: 3.27

Bachelor of Science in Electronics and Communication Engineering (2002

-2006)

Birla Vishvakarma Mahavidyalaya, Sardar Patel University, V.V.Nagar,

Gujarat, India

GPA: 3.12

SELECTED STRENGTHS AND SKILLS:

. Hardware Descriptive Languages: VHDL, Verilog HDL

. Testing instruments: Signal generators, Oscilloscopes, DMM

. Design: PSPICE, MATLAB,LASI, Smartdraw, M.S VISIO

. Hardware tools: OrCAD Schematic Capture, Cadence Verilog-XL, ModelSim

SE, Xilinx ISE, Altera Quartus & Timing Designer

. Programming Language: C,C++,Assembly level language

. Processors: Intel 8051 Microcontroller, Intel 8085 & 8086

Microprocessor

. Scripting language: Perl, Python

. Effective written and verbal abilities.

. Strong organizational and interpersonal skills.

SENIOR DESIGN PROJECT:

Automated ON-OFF Appliances:

A device uses Atmel microcontroller 89C52, RTC, LCD, 4x3 keyboards. The

whole peripherals are interfaced to the microcontroller 89C52. In this

project, RTC, The Heart of the project is programmed using Verilog HDL.

The data (when to turn on/off the appliances connected) is entered

using keyboard and that data is displayed on the LCD. The date and time

is fed to RTC and it starts counting the clock and when it comes to

know about the date and time entered i.e. when to turn on/off the

appliances is arrived, it gives a signal to microcontroller, which

performs the programmed task.

GRADUATE PROJECTS:

Encryption/Decryption:

Created a code for the five modules namely DES (top-level module data

encryption standards), Function, S-box, Key and constant using VHDL.

The project finds an application in communication field.

High speed 32-bit multiplication using pair recoding algorithm:

Designed High Speed Multiplication unit and coded it using Verilog

HDL giving a result approximately 50% faster than a regular

multiplication unit.

WORK EXPERIENCE:

ERICSSON (May 23 2011 - Present)

. Working as contract RF engineer.

. Understand client's needs to add channel and frequency to the base

station control centre to prevent the call drop and interference

problems.

. Update the current equipments of base station to more energy efficient

and cost effective equipments.

. Perform the CFR analysis to find out the way to reduce the cost and

provide the simple solution to the call drop and interference

problems.

SHIVAM ELECTRONICS (Jan 2006 - July 2007)

. Worked as a FPGA design Engineer, Test/Verification engineer.

Responsible for converting portions of a preliminary ASIC design into

a Xilinx Virtex family FPGA for use in a development system. Tasks

include Verilog RTL re-design of a memory arbiter, FPGA device

selection and pin out, synthesis, layout, RTL and gate level

simulation, and timing analysis. Tools used include Modelsim,

Leonardo Spectrum for synthesis, and Xilinx Alliance for place and

route.

. Designed a PCB using the latest protel software and ExpressPCB to

create a layout of the circuit.

. Handle the tasks of designing hardware test strategy and documentation

for variety of security solutions to support the objectives of project

and product development

. Responsible for creating test specifications and plans from high level

project documentation

. Perform the tasks of developing and implementing test strategies for

product and project

. Handle responsibilities of identifying and verifying new hardware

products

. Liaise directly with the development team to provide support for

ongoing testing activities

. Undertake other tasks and responsibilities to achieve project or

corporate objectives from time to time

Einfochips Solutions, Ahmedabad (Sep'06 - Jan'07)

. Worked as a Trainee Hardware design/verification engineer.

. Learned a Cadence allegro tools for testing the Asic functional

design and assisted sr. Asic engineer in designing and testing the

model.

. Handled the tasks of designing hardware test strategy and

documentation for variety of security solutions to support the

objectives of project and product development.

. Created test plan and documentation of test specifications from high

level project.

Embelink Electronics, Ahmedabad (Feb'07 - July'07)

. Worked as a trainee FPGA/ASIC design/test engineer.

. Provide analysis related to the design, development, and

implementation of hardware products

. Assist senior hardware engineer in developing test strategies, devices

and systems

. Perform stress and performance tests on a variety of computer hardware

including circuit boards, processors and wiring

. Participate in the design, research, development and modification of

information processing hardware, systems and electrical components

. Conduct basic testing of existing products to diagnose malfunctions

and make routine improvements or modifications to produce desired

results

. Evaluate design and test data as well as prepare technical

specifications and reports

. Analyze and assist in developing approaches to meet production

requirements for new or improved products and processes.

CALIFORNIA STATE UNIVERSITY, NORTHRIDGE (July'10-Dec'10)

. Worked as an Associate Hardware test & design engineer. Designed the

Data acquisitions architecture using OrCad capture by cadence. Code

this project using Xilinx Navigator tools by Verilog HDL, Simulated,

Synthesized and Implemented the program on Xilinx SPARTAN 3 kit and

debug. Carried out the PCB layout of the design using Multisim.

LANGUAGES KNOWN:

Fluent in English, Hindi, Gujarati and Basic Spanish

EXTRA-CURRICULAR ACTIVITIES:

. Presented a paper on Anti-stealth technology in technical paper

presentation fare organized by ISTE (Indian Society for Technical

Education) on March 31st, 2005.

. Participated in the workshop on advances in mathematical modeling and

simulation held on Nov 13th, 2003.

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