John Bantner

** ****** ***** ****

Jacksonville, OR 97530

Cell 541-***-****

abha89@r.postjobfree.com

Position: FPGA/system/circuit designer

Tools:

VHDL, Verilog, Abel, CPL, Warp and Palasm (hardware description

languages)

Orcad, Viewlogic, Dx_Designer, Cadence, Schedit, Case (schematic entry programs)

Modelsim, Viewlogic and Orcad (simulators)

Synplicity, Xilinx XST and Lattice Precision (synthesizers)

Meta (emulators)

C, assembly, microcode and python (programming languages)

Xilinx, Altera, Lattice and Actel (FPGAs)

Since 1989 all designs have been FPGA based and simulated.

Experience:

10/09 – Present Fairchild Camera, Milpitas, CA

Senior Systems Engineer – Doing system design and hardware design of a low noise (16

bit) CMOS camera for scientific applications using a camera link interface. The design is FPGA

based (Spartan 6) and includes bad pixel correction, offset and gain corrections/pixel, hi and lo

gain blending, binning, and 16 possible ROI. The design also included a high speed internal

block transfer buss for image processing and a PWM controller for a peltier TEC that was

maintained at a camera temperature

of +/ .05C.

12/07 – 03/09 Gatan, Pleasanton, CA

Consulting Engineer – Did system design and hardware design of a low noise (16 bit) CCD

camera for electron microscopes. Did both analog and digital design. The design was FPGA

based (virtex 5) and included horizontal overscanning, vertical overscanning, and digital CDS for

increasing the number of effective bits. The design also included a DSO(digitals sampling

oscilloscope) in the FPGA to allow tuning of the CCD drive signals while the camera was cooled

and in a vacuum. All CCD timing was programmable by use of memory mapped execution tables

that resided in the FPGA. The FPGA controlled all CCD clocking signals to a Resolution of 75

pico seconds. All of the advanced features

of the Vertex5 were used in this design.

10/06 10/07 Lightfleet, Camas, WA

Consulting Engineer – Did system design and hardware design of a super computer using a

novel all to all interconnection scheme. Did FPGA designs for direct high speed switching (10

Gbs) between any source computer blade and possibly multiple destination computer blades.

Implemented

Lattice FPGAs in both verilog and VHDL. Lattice was used because it offers a large number of

high speed serial ports.

7/04 present KeyTell, Inc Jacksonville, OR

Consulting Engineer Doing system design and hardware design of a programmable USB

keyboard with individually illuminated keys. Key intensity not affected by number of keys

illuminated. FPGA design includes multipliers and block RAMS and is implemented in VHDL,

modelsim and Xilinx XST synthesizer.

10/05 3/06 Grass Valley, Beaverton, OR

Consulting engineer Did hardware design of a video compression/decompression server

for driving projectors for the movie industry. FPGA design done in Verilog. Schematic entered in

Cadence.

7/05 9/05 Liposonix Bothell, WA

Consulting Hardware Engineer Designed vga/dvi display system and process control for

medical therapy instrument. FPGA done in VHDL, modelsim and Xilinx XST synthesizer.

12/03 7/04 Infact Data Beaverton, OR

Consulting Hardware Engineer/FPGA Designer Did system and hardware design of a

USB based 48 channel industrial monitoring unit which had a unique command structure

whereby any channel (under program control) could control the operation of any other channel.

Design included a DSP, large Xilinx FPGAs and analog design. FPGA done in VHDL, modelsim

and Xilinx XST synthesizer.

7/01 12/03 Engineering Design Team Beaverton, OR

Senior Engineer Did system and hardware design of PCI based image processing

system. Designed high speed 1k x 1k camera as front end for FPGA controlled system. ASCII

commands controlled the camera operation. FPGAs done in VHDL, modelsim and synplicity.

1994 6/01 SRC Vision Medford, OR

Consulting Engineer Did system and hardware design of entire PCI based color image

processing system in which various items on a conveyor belt were sorted on the basis of color

and/or shape. Items included wood chips, tobacco and produce. Pipelined design that included

linear CCD cameras, camera controllers, frame buffers, normalization, LUT thresholding,

hardware implementation of image processing algorithms, DSP hardware and air valve controllers

that ejected specified items from belt.

Design incorporated linear CCD imaging arrays, large Xilinix FPGAs, large VRAMs, large

DRAMs, DSPs. Customized PCI interface implemented in a Xilinx FPGA.

1997 1998 Metalithic Systems Sausalito, CA

Consulting Engineer Did system and hardware design of PCI based multimedia system.

Design included a customized processor with proprietary instruction set in a fully simulated Xilinx

FPGA. The PCI

interface used an AMCC PCI interface IC.

1993 1994 ASI Salem, OR

Consulting Engineer Did system design, hardware design and programming of

microcontroller based auto security system and associated microcontroller based programming

units.

1989 1993 IIMorrow/United Parcel Service Salem, OR

Senior Engineer Did system design, hardware design and debugging of the following:

a high speed (100 in/sec) label reader that used DSP, FFT and

correlation ICs interconnected by large Altera FPGAs along with standard

PALs. Input was 4096 pixel linear CCD. This label is currently on all UPS boxes and

is distinguished by a bulls eye surrounded by dots.

an 8 channel communications controller for a VME bus system. Used

large Altera PLDs and a 8051 controller. Wrote the assembly language code for

the 8051.

redundant 486 based CPUs for VME bus system using TI PC chip

set and large Xilinx PLDs for glue logic.

1975 1989 Information International Culver City, CA

Senior Engineer Did system design, hardware design and debugging of the following, all of

which were digital:

5 64 Mbyte frame buffer for real time rotating and mirroring of large pages.

Rotation was accomplished by a 16 bit bit slice micro processor. Also wrote

the bit slice microcode.

6 2k pixel x 1.5k line CRT display controller with 2 Mbyte frame buffer using

a 68000 CPU, a 68000 compatible ACRTC display controller and a 68000

compatible DMA controller. Included a bit slice microprocessor for

hardware windows and fast block transfers. Also wrote the bit slice microcode.

7 high resolution font to rasterized gray level converter using bit slice

microprocessor. Also wrote the microcode.

8 high quality character generators for photo typesetters

9 high speed character generators for photo typesetters

10 vector generators for photo typesetters

11 line art generator for phototypesetter

12 halftone dot generator for phototypesetter

13 front end system (16 terminals) for photo typesetters

14 page scanner using CCD as input device

15 interfaces to the VME bus for the following devices:

Xerox, Printware and Benson Varian printers

Hewlett Packard scanner

Did hardware design and debugging of the following:

16 high speed optical character recognition system

17 image processor containing approximately 3000 ICs, 30% of which were

running at 40 Mhz

1981 1985 Systems Interface Specialists Upland, CA

Vice President of Engineering Did system design, hardware design and debugging of the

following for mainframe computer:

18 front end (128 terminals)

19 main memory (16 Mword of 36 bits/word)

20 DMA channels (multiples of 4)

21 instruction prefetch for cpu performance acceleration

22 tape controller and line printer controller

(This work was undertaken in my off time with the consent of my full time employer, Information

International.)

Education: BSEE San Jose State, San Jose, CA

35+ graduate credits (Electrical Engineering/Hardware Design) UCLA, Los

Angeles, CA

References:

Paul Mooney 925-***-**** business senior scientist

Bob Edwards 925-***-**** business engineer manager

Tod Santana 541-***-**** business engineer manager

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