Design Engineer

CHANDNI PATEL

*** * ******** ******, ********, CA 91801

551-***-****, abh616@r.postjobfree.com

OBJECTIVE: To contribute technical skills and strong commitment in the

field of Hardware Engineering.

EDUCATION:

. M.S in Electrical & Computer Engineering, San Diego State University,

CA. Dec 2009 GPA 3.55

. B.S in Electronics & Communication, C. K. P.C.E.T, India.

June 2005 GPA 3.50

SUMMARY:

. Proficient in Digital/Analog Circuit Design, CMOS Design, RF Circuits

and Systems, and C programming.

. Proficient in Schematic Capture, Layout and Simulation tools such as

Cadence Virtuoso, Allegro, ELDO, H-SPICE, and P-SPICE. Synthesis tools

such as ModelSim, Xilinx ISE. Familiarity with Linux/Unix.

EXPERIENCE:

Electronics Engineer (Research and Development): AMREL Inc.

March 2010-Present

. Design, test and troubleshoot electronics hardware at component, PCB,

motherboard, and system level. Soldering (SMT and THT) circuits.

Read/edit PCB schematic and layout, and solve signal integrity issues.

. Record test performances using Oscilloscope, Multimeters, Spectrum

Analyzer, and Signal Generators.

. Develop, test, and debug prototype units, system integration, and

record technical data like assembly and testing procedures according

to ISO process. Work with Sales, Marketing and customers on customized

specifications.

Teaching Assistant (Digital Logic Lab): San Diego State University

May 2008-Dec 2008

. Conducted laboratory for a class of 30 students, introduced tools like

Xilinx ISE, and Modelsim. Assisted in VHDL programming, implementation

on Spartan FPGAs and interfacing FPGAs with VGA and Keyboard.

RESEARCH PROJECT (CIRCUIT DESIGN):

(March 2008-Dec 2009)

Three-Stage Wideband Transimpedance Amplifier (TIA) in AMS BiCMOS

Technology for Optical Receivers

. First-Stage: Common Base input buffer stage designed to reduce the

influence of photo detector capacitance.

. Second-Stage: Designed a Fully Differential Amplifier with shunt

feedback to achieve stability and immunity against noise.

. Third-Stage: Common Source amplifier designed with Inductive coupling

to achieve a large bandwidth of 4GHz.

. Biasing Stage: Designed a Current Mirror to set the bias voltages for

input stage.

. Performed Small Signal Analysis of individual stages, and Overall AC

and Transient analysis to measure Gain, Group Delay, -3dB bandwidth,

Eye-Diagrams, and noise. All simulations carried out in H-SPICE.

RELEVANT PROJECTS:

Analog Design Projects

. Layout of VGA - Complete layout of Variable Gain Amplifier (VGA) drawn

in AMI 0.5um CMOS Technology. Verified it by performing LVS, DRC.

Extraction of parasitic done using PEX tool from Mentor Graphics.

. Two Stage Op-Amp - Designed a two stage Op-Amp in TSMC 0.18um using

compensation techniques to achieve stability with a given resistive

and capacitive load.

Digital Design Projects

. Digital UART - Designed a Digital Universal Asynchronous

Receiver/Transmitter by integrating various different modules of Clock

Generator, LFSR, Parity Generator, Comparator, and Parallel to Serial

Convertor using VHDL programming. Synthesis, place and route, and post-

map simulation carried out in Xilinx.

. Transistor Level Design - Transistor level design and layout for 3-

input NAND and NOR gates in Mentor Graphics ELDO and IC Station.

TECHNICAL PROFICIENCIES:

. Programming Languages VHDL, Verilog, MATLAB, C

. Tools Cadence Virtuoso, Spectra, Allegro, H-

SPICE, P-SPICE, Mentor Graphics IC Station,

ELDO, Leonardo Spectrum, Xilinx, ModelSim

Simulator, MS Office

. Lab Equipments Spectrum Analyzer, Oscilloscope, Signal

Generator, Digital Multimeter (DMM)

RELEVANT COURSE WORK:

Signal Integrity, Device Physics, Digital Communication, Digital Logic

Design, Power Electronics, CMOS VLSI Circuit Design, RF Microelectronics,

Microcontroller Circuits, ASIC Design, Digital Signal Processing, Digital

Circuits.

HONORS:

. Recipient of David G Fleet Scholarship for academic excellence, San

Diego State University. (May 2007)

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