*. Personal

Reza M. Rad

Phone: 240-***-****

Email: abh51q@r.postjobfree.com

Mail: 8388 Montgomery Run Rd, Apt E, Ellicott City, MD 21043

Visa Status: Permanent Resident (Green Card)

2. Skills & Keywords

Semiconductor professional with 4 years of experience as ASIC/FPGA RTL

SOC designer and DFT engineer with strong backgrounds in communication

systems and digital signal and image processing

Keywords:

ASIC, SOC, FPGA

RTL, VHDL, Verilog, Synthesis

DFT & Test

ATPG, JTAG, IEEE1500, BIST,

CAD, EDA, DPPM, ATE, DFM

Integration, pattern generation,

New product bring up, silicon debug,

Cadence: Encounter Test, First Encounter RTL to layout, ICFB, Virtouso,

Assura

Mentor: TestKompress, MBISTArchitect, BSDArchitect, FastScan, DFTAdvisor

Xilinx ISE, Xilinx EDK/SDK, Altera Quartus, Modelsim

C/C++, perl, tcl and other scripting languages

3. Professional Experience (~4 years)

Maxlinear Inc.

2010-present ASIC DFT engineer

DFT architecting, Developing test features such as scan, test

compression, MBIST and Boundary scan for multimedia SOCs, test

pattern development and verification on ATE,

First silicon bring up of a GPS SOC

Test verification for a digital TV SOC

Evaluated redundancy and repair options for embedded on chip memories

IGI Technologies Inc.

2008-2010 Hardware Engineer

Architect and RTL designer of a hardware acceleration engine for 3D

image registration implemented on Altera Stratix II FPGA,

RTL and gate level simulations on ~300k gate design at ~200 MHz

Synthesis, floor-planning and timing verification

Revised the architecture and added new features that boosted the

performance by a factor of 6

Used DDR2 and PCI interfaces

PCTEL Inc.

Summer 2008 Intern

Developed DSP code on TI processors for a wireless scanner system

Developed a deeper understanding of aspects of wireless

communication systems and protocols

Iran Telecommunication Research Center

1997-1999 Hardware Engineer

Development of parts of baseband section of a radio communication

system on FPGA, RTL design, synthesis and simulation, PCB design and

implementation

4. Academic Experience

University of Maryland Baltimore

2008-2010 Faculty Member

Taught a graduate level course in ASIC design verification and

testing

Taught graduate and undergraduate courses in RTL desing and

implementation of digital systems on FPGA

Design and Implementation of an on chip time measurement unit (TDC)

and its application as a physically unclonable function (PUF) for

hardware security and IP protection in ASICs and FPGAs

University of Maryland Baltimore

2005-2008 Research Assistant

PhD dissertation: a novel defect detection and localization and

failure analysis method based on regional transient current (Iddt)

analysis

Bu-Ali Sina University, Iran

2001-2005 Faculty Member

Taught a number of courses including microprocessor systems and

digital design with VHDL

University of Tehran

1998-2001 Research Assistant

Master Thesis: RTL design of a VLIW pipelined architecture for a

high performance DSP and FPGA implementation and emulation

Selected Publications

R. M. Rad, J. Plusquellic, M. Tehranipoor, "An Evaluation of Power

Signal Methods for Detecting Hardware Trojans under Real Process and

Environmental Conditions", IEEE Transactions on VLSI Systems, 2009.

R. M. Rad and Jim Plusquellic, "A Novel Fault Localization Technique

Based on Deconvolution and Calibration of Power Pad Transients

Signals", Journal of Electronic Testing Theory and Applications, 2008,

pp. 169-185, vol. 25, No 2-3, June 2009.

R. M. Rad and Jim Plusquellic, "Temporal Analysis and Spatial

Deconvolution of Power Pad Transients Signals for Fault Localization",

IEEE workshop on defect based testing (DBT'07), 2007.

R. M. Rad, X. Wang, J. Plusquellic, M. Tehranipoor, "Power Supply

Signal Calibration Techniques for Imroving Detection Resolution to

Hardware Trojans", IEEE Interantional Conference of Computer Aided

Design (ICCAD), 2008.

M. Tehranipoor and R. M. Rad, "Built-in Self-Test and Recovery

Procedures for Molecular Electronics-Based NanoFabrics," IEEE

Transactions on Computer Aided Design of Integrated Circuits, vol. 26,

no. 5, pp 943-958, 2007.

M. Tehranipoor and R. M. Rad, "Defect Tolerance for Nanoscale Crossbar-

based Devices", IEEE Design & Test of Computers, vol. 25, issue 6,

2008.

R. M. Rad and M. Tehranipoor, "Evaluating Area and Performance of a

Hybrid FPGA with Nanoscale Clusters and CMOS Routing", ACM Journal on

Emerging Technologies in Computing Systems (JETC), vol. 3, issue 3, no.

15, 2007.

R. M. Rad and M. Tehranipoor, "A New Hybrid FPGA with Nanoscale

Clusters and CMOS Routing", in proc. of ACM IEEE Design Automation

Conference (DAC), pp. 727-730, 2006.

R. Shekhar, W. Plishker, R. M. Rad, "Hardware-Accelerated On-Demand

Rigid and Non-rigid 3D Image Registration", accepted to SiiM 2010

Annual Meeting

G. R. Chaji, R. M. Rad, S. M. Fakhraie and M. H. Tehranipour, eUTDSP: A

Design Study of a New VLIW-Based DSP Architecture, in proc. IEEE

International Symposium on Circuits And Systems (ISCAS 03), Bangkok,

Thailand, vol. 4, pp. 137-140, 2003.

5. Education

Ph.D. Computer Engineering, University of Maryland Baltimore, 2008.

M.S. Computer Engineering, University of Tehran, Iran, 2001

B.Sc., Electrical Engineering (Communications), University of Tehran,

Iran, 1998

Contact this candidate