Design Engineer Project

Vivek Rajeev Ravirala

Career Summary

Professional

Experience

Mobile : +65-86984796 ( Singapore )

+91-949******* ( India)

Email Id : ************@*****.***

- A self motivated and result focused individual with four year and five

months of experience in Physical Design currently working with Mediatek

as a consultant from Uniconnect

- Thorough understanding and hands-on experience of industrial CAD tools

for ASIC/FPGA design flow (from RTL to GDSII)

- Hands on experience in both Analog Layout and Digital Layout design in

real time projects

- Expertise in various back end activities ranging from synthesis to

tapeout including the design activities such as Synthesis, Floorplanning,

Clock Tree Synthesis, Place& Route and Timing analysis, DRC LVS solving.

- Worked on latest technologies of 28nm and 20nm in various projects on

complex blocks with a gate count of 1.4 million

- Interested to work in the role of a Physical Design Engineer that

leverages my knowledge and skills to contribute to the growth of the

organization

Projects at Mediatek Pvt Ltd May2014

-present

I am currently working as a Physical Design Engineer at Mediatek as a

consultant from Uniconnect. I have worked on designing DDR RAM memory chips

from sub-macro level to top hierarchy and blocks related to PCIE express.

The following are the projects in detail.

Overview: A DDR block with 300k gate count, 533Mhz design, TSMC 28nm LP

technology

The block is challenging in terms of building the clock tree and

achieving very less skew within the DDR.

Overview: A PCIE block with 1.4 million gates 35 macros, TSMC 28nm LP

This block is handled from initial stage to tapeout. The clock

building and achieving skew with the given clock was critical. Handling

interface communication was a tough task.

Projects at AMD India Aug2010-April 2014

I have worked on various GPU projects and handled multiple blocks

with Low Power technology during my work period at this company. The

following are the projects done at AMD as a contractor from Soctronics.

Overview: A GPU block with 300k and 500k gates 10 macros, 953Mhz, GF 20nm

LP

I have handled the block with two clocks which are critical in

meeting timing. Responsible for taking the block from Place and Route

towards tapeout. Helped in guiding one critical tile towards tape-out by

fixing timing.

Overview : A GPU texture block with 650k gates 34 macros, 939MHz, TSMC 28nm

LP

I have handled two texture cache tiles the project. Responsible for

completion of tiles from Place and Route to tapeout. Interface

communication was critical for one of the blocks. Required careful

communication with FCFP on pin placement and module communication

Worked as a mentor in making people understand various DRC rules and

fix them with ease. Worked with flow issues for DRC and LVS and helped them

resolve before hand

Overview : A GPU sequencer block with 600k gates 30macros, 940MHz, TSMC

28nm LP

I have handled a Texture cache and DFT tile in this project. Worked

from Place and Route to tapeout.

Fixing timing for many clocks handling skew and DRV were critical in

the project.

Education

Awards and

Recognitions

Key Skills

Social Skills

Personal

Interests

Overview: A GPU texture cache with 700k gates 60 macros, 953MHz, TSMC 28nm

LP

I have handled two large texture cache tiles in this project. I have

handled the tile from Floorplan stage to tapeout. Block is powergated, ONO

in nature.

Congestion and interface timing and DRC were the main issues in this

project. Worked towards closing the tiles on time in a critical schedule.

Supported Physical Verification team in this project for a team of

twenty members in helping them understand DRC errors and LVS issues.

Handling critical tiles in tight schedule and successfully driven them

towards tapeout.

Overview: A GPU sequencer block with 350k gates, 30 macros, 930MHz,TSMC

28nm LP

In this project I handled two sequencer blocks of same logic with

different Height and width. I had done from Floorplanning to GDSII for

these two blocks.

Module communication was critical for these blocks to fix timing.

Creating bounds for these helped in resolving the issue.

- Diploma program in Analog Layout and Physical Design from VEDA IIT Pvt.

Ltd, Hyderabad.

- Bachelor of Technology in Electronics and Communication Engineering from

Jawaharlal Nehru Technological University, year of 2010 in Distinction

- Awarded Spot Recognition Award for contribution towards work from AMD

Hyderabad.

- Winner of area level International Speech contest at Toastmasters

Hyderabad

- Vice-President Public Relations of Secunderabad Toastmasters

EDA Tools

- Synthesis Tools: Synopsys Design Compiler

- Physical Design Tools: Synopsys IC Compiler, Cadence Encounter

- Timing Analysis: Synopsys PrimeTime

- Layout Tool: Calibre, Laker

Scripting Languages

- TCL

- PERL

- I am experienced at communicating with people from different parts of

world and working with them.

- I am part of Toastmasters communication program where I have achieved

Competent Communicator award by Toastmasters International

- Ability to analyze the results of my work independently for the projects

and associate with my co-workers to complete project on time

Hobbies Sketching, Public Speaking, Blogging

Interests Trekking, Nature lover, Teaching

Organizations Toastmasters, Youth for Seva

Professional Blogs vlsi-freaks.blogspot.in

Other Blogs eagleonfire.blogspot.in

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