Engineer Design

RICARDO L. CAZARES

**** ******* ***** 858-***-****

San Diego CA 92130 abh2lp@r.postjobfree.com

OBJECTIVE

Obtain a position as a Senior Analog IC Design Engineer for analog/mixed

signal products

QUALIFICATION SUMMARY

Advanced Design/Analysis Skills: CMOS, Bipolar and biCMOS; high-speed

(10Gbps) transistor-level analog; high-performance, low noise PLL and

DLL; low-power analog and RF design; CMOS fabrication processes;

layout tradeoffs for performance, precision, and size; laboratory

measurements of analog circuits; parasitic capacitance, resistance,

power routing and package analysis; and transmission lines theory

Software/Tools: Cadence Spectre, Mentor DAIC and Eldo, HSPICE, Diva, and

Calibre; Virtuoso and ICStation layout; and Unix, Linux, Windows,

Macintosh platforms

Leadership/Other: Project management, engineer employee supervision, U.S.

Secret Security Clearance, U.S. citizen, bilingual in English/Spanish,

and technical report writing

PROFESSIONAL EXPERIENCE

RAMTRON INTERNATIONAL, Carlsbad, CA 2009

Consultant

Reported to Director of Engineering - Designed low-power 2MHz oscillator

with optimum power-supply rejection for RFID application using TI .18um

process.

. Designed trim circuitry to account for process variations

. Completed project with abundant margin over temperature

NEOLOGY, Poway, CA 2005 - 2009

Senior IC Design Engineer

Reported to VP of Engineering, Director R&D - Sole engineer responsible for

all facets of integrated circuit design for low-power RFID tags, including

fabrication process evaluation, analog circuit design and simulation,

circuit layout, and circuit test and evaluation.

. Evaluated potential foundry partners for compatibility to

specific design requirements, specifically Schottky diodes

and low-power non-volatile memory

. Designed transistor-level analog circuits using Mentor

ICStudio, including charge pumps, voltage multipliers,

demodulators, voltage regulators and precision delay circuits

. Performed physical layout of analog blocks and verified with

Calibre

. Designed and implemented test structures to evaluate circuits

and devices

. Evaluated test structures and on-chip blocks on Suss

microprobe station

. Documented and analyzed test results and design targets

. Supervised lab technician handling building, testing and

evaluating test structures

SEQUOIA COMMUNICATIONS, San Diego, CA 2004 - 2005

Consultant

Reported to Director of Engineering - Designed clock-generator DLL circuit,

using 26 MHz reference to generate 13 MHz, 26 MHz and 104 MHz clock

outputs, using IBM's 7WL, .18um biCMOS process.

. Incorporated programmable skew option with 1.2 ns resolution

maintaining a near 50% duty cycle

APPLIED MICRO CIRCUITS CORP., San Diego, CA 1999 - 2003

Senior Design Engineer

Reported to Bipolar Design Manager - Designed high-speed bipolar (10Gbps)

transmitter/receiver chip sets.

. Designed 10Gbps (OC-192) low-jitter clock and data CML

output, digital phase-frequency detector block and other high-

speed analog cells

. Coordinated top-level schematics on 30Mbps to 2.7Gbps

continuous rate Clock and Data Recovery unit

. Managed characterization of OC-192 transmitter as liaison

between Design Engineering and Product Engineering

. Created comprehensive yield and data analysis reports using

DataConductor

. Produced functional products on first pass

METAFLOW TECHNOLOGIES, INC., San Diego, CA 1996 - 1999

Senior Design Engineer

Reported to Engineering Manager - Created low-power Pentium-class

microprocessor using .25um CMOS.

. Coordinated layout and floor plan of complex data path logic

blocks

. Verified performance for logic blocks using Pathmill

. Supervised interns in design group

APPLIED MICRO CIRCUITS CORP., San Diego, CA 1983 - 1996

Senior Design Engineer

Reported to Engineering Manager - Designed, developed, characterized,

maintained semi-custom gate array-based libraries.

. Developed three bipolar gate array families, including macro

cell libraries, reference generators, chip layout and floor

plans

. Designed semi-custom bipolar PLL clock synthesis and recovery

circuits

. Supervised engineering group to develop automated methodology

for design and layout of gate array-based PLL circuits

. Designed and implemented scribe-lane "AC speed monitor"

circuit used as wafer sort benchmark tool

EDUCATION

BS, Electrical Engineering-University of California, San Diego

Currently pursuing RF Engineering Certificate through UCSD Extension

MEMBERSHIP / INTERESTS

IEEE, tennis, fitness, snowboarding

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