Engineer Design

JOHN EADES

**** ********* ****

H: 512-***-****

Austin, TX 78748-5015

C: 512-***-****

abh24v@r.postjobfree.com

SUMMARY

Detail oriented Senior/Lead IC Layout Designer/Engineer with several years

of successful CMOS experience. Organized, proactive, assertive, and self

motivated problem solver with experience in many areas of design. Has the

ability to learn quickly and achieve company objectives. Has experience in

multi-cultural environments with a broad array of individuals in cross-

functional multi-continental teams. Has a good communication, teamwork and

debug/analysis skill for layout designs and technology files. Proficient

in MPU, DRAM, SRAM, CACHE, PDA, read channel and chip set designs.

Document design and control experience for discrete manufacturing.

. Chip Floor Planning

. Analog and Digital Layout

. Cadence Virtuoso

. Mentor Graphics

. Calibre DRC / LVS / ERC

. Hercules DRC / ERC

. Auto Place & Route

. Avanti Apollo Router

. SKILL and AMPLE

PROFESSIONAL EXPERIENCE

Freescale Semiconductor, Austin, TX

2006 - 2009

Senior Layout Designer

. Contributed to the development of the 32nm SOI process design rules for

the R&D alliance with IBM.

. Designed complex standard cell layouts in 65nm, 45nm and 32nm SOI and

Bulk processes.

. Modified skill scripts for library management.

. Worked closely with customer on design.

. Contributed to the standard cell library management specifications and

procedures document.

. Reviewed engineering drawing and designs to ensure adherence to the

established specifications and standards.

Fitness Factor USA Inc., Austin, TX

2002 - 2006

President

. Developed business plan for goal setting, investors, and future

franchising.

. Developed marketing plan that created local business partners and boosted

sales by 30%.

. Designed and created marketing brochures and materials.

. Made management decisions, directed advertising and marketing.

. Negotiated contracts.

Advanced Micro Devices, Austin TX

2000 - 2002

Contract Senior Mask Designer

. Designed custom layout for chip set designs.

. Experience with Apollo router at block and chip level.

. One of the key players on Golem and OPUS chip sets, providing layout

support.

IBM, Austin TX

1997 - 1999

Contract Senior Layout Designer

. Designed the CACHE circuit for IBM's 630 group.

. Assisted in the design of complex adder circuit for the

Gigahertz processor development group.

Advanced Micro Devices, Austin TX

1996 - 1996

Contract Senior Mask Designer

. Designed layout of CACHE for K7 test chip.

. Worked several months of approximately 70+ hour weeks to re-vamp of K5

microprocessor.

Cirrus Logic, Austin TX

1994 - 1996

Senior / Lead Layout Designer

. Created analog and digital layouts, periphery and top level

interconnections.

. Chip and block planning.

. Mentored junior layout designers

. Major contributor in many Crystal/Cirrus read channel designs.

Micron Technology, Boise ID

1988 - 1993

Senior / Lead Layout Designer

. Lead layout for five designers on Micron's Triple Port DRAM.

. One of the key players in the design of the first 128k CACHE Data Ram for

Compaq Computer.

. Designed several Micron DRAM's including 1MEG, 4MEG, and 16MEG.

. Responsible for pad cell layouts, standard cell layouts, arrays and

periphery layout designs.

Intel Corp., Hillsboro OR

1988 - 1988

Contract Mask Designer

. Layout support for i960 RISC CPU's data path.

Zenith Microcircuits, Elk grove Village, IL

1986 - 1987

Design Engineer

. Engineered and designed resistor and capacitor networks for hybrid

circuit ceramic substrates.

. Designed detailed control documents for the processing and manufacturing

of the specific circuit designs.

EDUCATION

Ivy Tech, Kokomo, IN

AAS in Electronics Technology

US Army Engineer School

Diploma in Mobile Power Generation

Additional Classes through:

University of Maryland

Central Texas College

University of Idaho

Indiana University

Stanford University non-credit through Micron Technology

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