Engineer Design

KAVITA BANSAL

**** ********* **, *** # **

Santa Clara - 95051

CALIFORNIA

+1-408-***-****, +1-408-***-****(M)

******.*.******@*****.***

Objective:-

To obtain a challenging position as a hardware design engineer at a reputed

organization, that could give me opportunities to develop and exploit my

skills and knowledge acquired over years in this field and hence

contributing to the company's growth.

Summary:-

More than 4 years of experience in SOC design and implementation for

wireless communication chips used in base-stations as well as mobile

handsets.

Expertise: Design for Test

Skills:

. Knowledge of VLSI Design, VLSI Fault Models.

. DFT and BIST techniques.

. Scan insertion using Synopsys DFT compiler.

. Usage of Synopsys TetraMax tool for pattern generation and coverage

estimation for Stuck-At faults, IDDQ, Transition and Bridging fault

models.

. Pattern Conversion using XUtile.

. IEEE 1149.1 JTAG Boundary Scan insertion using Synopsys BSD compiler.

. Static Timing analysis using Synopsys Primetime.

. Formal Verification using Synopsys Formality.

. DFT Verification using Synospsys VCS and Cadence NCSIM.

. Handoff and signoff flows using Synopsys Kits.

. RTL coding in verilog and VHDL.

. Synthesis using Synopsys Design Compiler.

Professional Experience:-

Senior Hardware Design Engineer, Wireless Mobile and Multimedia SOC design

group

ST-Ericsson, India (Jun, 2009 -

15th Jan,2010)

SOC - 240MHz mobile platform chip in 55nm technology:

Static timing analysis, handoff and signoff for all the test modes.

Complete support to back end for all their activities.

Design Engineer - II, Mobile multimedia and Communication group

STMicroelectronics Pvt. Ltd, India

(Oct, 2007 - May, 2009)

.

IP - 300MHz Communication infrastructure design chip in 65nm technology:

Responsible for all DFT activities of the team, which includes ATPG and

pattern simulations for transition and single stuck-at faults, Memory BIST

simulations to verify the BIST, bitmap and redundancy flows, etc. also

responsible for constraints development, handoff and signoff for all the

modes of the chip.

ASIC - 20Mn-gate (with 100 memories) 280MHz Wi-Max Chip in 90nm technology:

Lead the complete DFT implementation till the tape-out. Some of the

responsibilities

. JTAG and TAP controller insertion using Synopsys BSD Compiler.

. Scan Insertion and recognition flows using Synopsys DFT Compiler.

. ATPG Coverage and fault simulation using Synopsys tetramax for the

stuck-at, transition and bridging faults.

. Complete verification of chip in all the test modes. Developed test

benches and ran simulations (using Cadence NCSIM) for all ATPG modes,

BIST verifications and also BIST controller of ARM1176CM, analog tests

- ADC/DAC, PLL testing, compensation cell testing.

. Static timing analysis, handoff and signoff for all the test modes.

. Pattern Generation for all the test modes in different formats like

eVCD, WGL and STIL using tetramax and NCSIM. Pattern conversion using

Xutile.

Design Engineer - I, Wireless Infrastructure Design group

STMicroelectronics, India (July,

2005 - Sep, 2007)

ASSP - 65nm base band processor for wireless base stations:

As an individual contributor in DFT from our site handled the complex

design consisting of 2 DSPs and ARM11. This includes

. Writing test architecture and test mode controller specifications

outlining the test strategy and test requirements for various modules.

. Developed the Test Mode controller code RTL in verilog which included

BISTs for PLL and memory testing. Insertion of data registers for the

storage of BIST inputs and responses. Created an excel sheet for 16

test modes which could automatically generate the verilog output for

the test mapping of input/output ports.

. Synthesis of TMC and its integration with the functional netlist.

. Responsible for verification of all the test modes - VHDL testbenches

for PLL/DLL/compensation cells testing, test strategy for verification

of memories - BIST test mode, redundancy tests consisting of Single-

antifuse initial checking, its programming and soft reparability

strategy flows, bitmap mode. All BISTs worked at functional

frequencies (max 440Mhz) leading to the complexity of verification

through sysco and PLLs.

. Pattern Generation and conversion using Cadence NCSIM, Synopsys VCS

and XUtile.

. Static Timing Analysis and handoff for the BIST mode.

ASIC - 2Mn-gate 131MHz Voice over IP chip in 130nm technology:

Worked on the fault simulation flow and was successful in increasing the

ATPG coverage from 96.98% to 98.3%, removing a bottleneck in the project.

Established the handoff flow and ran in functional and all test modes.

Wrote a port2pin macro in excel which could automatically generate the

port2pin text file required as an input for the boundary scan insertion.

Established the Synopsys DFTMAX and on-chip Controller insertion flow which

could be used for reducing the tester volume and cost. Got the appreciation

award certificate for the successful completion of the project by ST

management.

Operating Systems:- Unix, Linux, Windows

Academic Qualifications:-

Pursing MS Electrical Engineering from Santa Clara University, Santa Clara,

CA

Post Graduate Diploma in Business Administration (July, 2006 - Oct, 2008)

from "Symbiosis Centre of Distance Learning" (specialization in Human

Resources)

B.E (Bachelor of Engineer) (July, 2001 - May, 2005) from "Punjab

Engineering College (PEC)", Chandigarh, Electronics and Electrical

Communication Engg. Received gold medals from PEC and Punjab University.

Industrial Trainings and Projects during B.E:-

Bharat Electronics Limited, Panchkula from 23rd May to 19th June, 2003 -

Worked on the V/UHF transmitters testing used for the ground to ground and

ground to air communication by the military.

Bharat Sanchar Nigam Limited, Chandigarh from 2nd June to 29th June, 2004 -

Study of telephone exchange functionality and various technologies

implemented in the networking.

Electronics Quiz Table "Status Indicator": To design an electronics quiz

table consisting of four participants.

Design of Digital Thermometer: To measure the temperature of the body and

display it through LCD.

Extra Curricular Activities:-

. Chairperson for the PEC chapter of "The Institution of Electronics and

Telecommunication Engineers" and Core member of the executive of

"Indian Society for Technical Education". Received a college color as

an honor for the achievements done by the chapter. Organized national

level symposiums, various quiz competitions, a digital design workshop

for the juniors, paper presentations in the tenure.

. Member of Student Council in college. Was a part of lot of college

level events.

. College Co-ordinator for National Service Scheme involved in helping

poor people. Formation of self help groups for bringing financial

independence to the women.

. Executive body member of Rotaract Club in college.

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