Design Assistant

Chao Zhang

*** *. ** ****** ****, Sunnyvale, CA**087 *********@*****.***

530-***-****

Objective: A versatile, analytical and hard-working Computer

Engineering professional with a practical hands-on approach, seeking an

entry-level engineering position to fully utilize my extensive knowledge

and excellent abilities in ASIC/FPGA

Computer Skills:

Programming Languages: VHDL, Verilog, Verilog-A, C language, Assembly

Operating System: Microsoft Windows (95/98/2000/XP/Vista/Win7) and UNIX

(Redhat/Fedora/Ubuntu)

Software: Cadence, NClaunch, SoC Encounter, RTL complier, Modelsim, HSipce,

ISE, Microsoft Office

Education:

Polytechnic Institute of New York University, Brooklyn, NY M.S. Computer

Engineering GPA: 3.8/4.0

. Winner of Graduate Center Merit-based Scholarship respectively in 2008

and 2009

East China Normal University, Shanghai, China B.S.

Microelectronics Class Rank: 5/55

Projects:

Memristor thermal sensor design:

Jan ~ May 2010

. Developed a new application of the fourth circuit element, Memristor,

combined with CMOS technology

. Design finalized as 1oC resolution in the range from -55oC to 150oC,

with 5.4umx3.4um area (TSMC_90nm)

. Created a device model formulizing memristor's thermal property

. Performed full ASIC design flow and wrote Master thesis paper

Network-on-Chip VHDL design:

Jan ~ Dec 2009

. Study high performance NoC structure supported by U.S. Army CERDEC

. As key VHDL designer, designed network interface (AMBA), switches and

buffer control (VoQ) modules

. Reduced latency of 4x4 NoC by 6 clock cycles, improved area/cost

efficiency by 30%, handled 3 types of bursts

. Comparison study between 2D-Mesh and Clos-network, following ASIC/FPGA

design flow

Steganography SoC implementation:

Jan ~ May 2009

. VLSI chip design carrying novel graphic encryption algorithm, which is

verified on software platform

. ASIC system level division and SoC architecture design, in a divide-

and-conquer manner

. Responsible for back-end process and research report writing as a team

player

32-bit ALU ASIC implementation:

Oct ~ Dec 2008

. Customized standard cells, schematics/layout design, Spice model

simulation, DRC and LVS

. Conducted compact layout manner, saving 50% area, chip is taped out

with MOSIS CMOS 0.25um

. Individually carried out ASIC flow (digital design)

Experiences:

Research Assistant, Polytechnic Institute of NYU, Brooklyn, NY

Jan 2009 ~ Aug 2010

. Fulfilled ASIC/FPGA design frontend responsibilities, including source

codes writing, algorithm verification

. Co-worked with ASIC backend, Schematic/layout design (Cadence

Schematic Composer and Virtuoso)

. Wrote technical report, debugging and testing, and address

presentation in group meetings

. Reviewed papers for conferences, such as ISCAS 2010, ISLPED 2010, VLSI-

SoC 2010, IC-FPT 2010, etc.

Teaching Assistant, Polytechnic Institute of NYU, Brooklyn, NY

Sep 2009 ~ May 2010

. Assisted professors during their lectures and lab sessions, prepared

course wares and paper works

. Supervised the students in lab sessions, and guided seniors and

juniors to learn ASIC design flow

. Graded homework, lab reports and examinations, and solved specific

problems

. Gave lectures on experiments and demonstrated the procedures on Xilinx

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