Design Manager

Carol Arnst

** ******** *****

Jericho, Vermont *5465

Home Tele.: 802-***-****

Email: **********@*****.***

Objective:

To provide skill and knowledge in layout design, contributing my best for

the company and its goals.

Summary:

18+ years experience in CMOS Mask Design.

Good knowledge of PLL's, math co-processors, IO Pads, sub-micron

technology, and EEPROM's, using custom, standard, and programmable cells.

Experience includes common-centroid layout, matching, shielding, and

design for manufacturing. Majority of design work has been in analog, but

have also done mixed signal.

Work well with other engineers and designers as well as independently. Job

duties included Cadence layout and XL, Virtuoso, Calibre DRC, LVS, bonding

diagrams, plotting, and documentation.

Open to learning new ideas and putting in the effort of completing layout

within schedule.

Experience:

Asic North

'10 July - '11 May

Layout for various IBM departments as con

CTG

'08 May - '08 Nov

Layout for test macros at IBM as contractor.

IBM, Long Term Supplemental

'04 - '07

IO Pad layout using Cadence tools and Synopsis verification.

Infineon/IBM Contract

'03 Jun. - '03 Aug.

SRAM Logic.

IBM, Williston, Vermont

'00 Jan. - '02 Jun.

ASIC Analog Digital Cores Group - Manager: Paul Allard

VLSI Mask Designer of PLL's.

Lattice Semiconductor, Hillsboro, Oregon

'94 Sep. - '95 Oct.

Cmos Designer on EEPROM circuits using Sun Workstation with Edge software.

Atmel, San Jose, California

'93 Sep. - '94 Sep.

Used Sparc20 Workstation using Cadence Edge software for CMOS design in

EEPROM Group. Technology used submicron and double metal.

Zilog, Campbell, California

'92 Apr. - '93 Sep.

VTI/Microvax and Sun Workstations with Edge software for design of Consumer

Product Group. Was also called upon to help overflow of work for analog

group. Completed training on OPUS software.

Weitek, Sunnyvale, California

'86 Jun. - '92 Apr.

Senior layout designer using custom and standard cells to develop VLSI math

coprocessors, floating point, and laser printer circuitry. Duties included

scheduling layout using Calma GDSII and Valid Construct software, plotting

on Synergy and Versatec plotters. Dracula drc and lvs checking, scribe, and

documentation. Comlpleted training in Cadence BPR and Unix. A minimum of

three designers worked on one VLSI circuit. This developed good

communication skill and coordination of duties among the designers. This

also gave me opportunities to design various areas of the chip such as back

plane, pads, data paths, fpu, registers, capacitors, timers, and

multipliers.

Advanced Micro Devices, Sunnyvale, California

'84 Mar. - '86 Jun.

Junior layout designer for Interface Bipolar Division. Duties included Cmos

layout, planning, drc, process, and pattern generation, plotting,

documentation, and archiving completed projects.

Education:

1983 - 1984: Institute for Business and Technology, San Jose, Ca.

Subject: NMOS and CMOS Design.

1968 - 1971: Cerritos College, Norwalk, Ca.

Subject: Data Processing and Dental Assisting

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