Design Electrical Engineer

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BHARGAV TANK

Address: *** ***** *** ** ***#17

Email: *********@*****.***

San Jose, CA 95112

Cell: 001-408-***-****

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Objective: Seeking a Fulltime/Co-op position as a Hardware/Test/Product

Engineer.

Educational Background:

. M.S in Electrical Engineer, Specialization in Analog/RF/Mixed Signal

Design. (Dec 2010)

San Jose state University, San Jose, California, USA

. B.E in Instrumentation & Control

(May 2007)

Dharm Sinh Desai Institute of Technology, Nadiad, Gujarat,

India

Employment & Experience:

. Test Engineering Intern at National Semiconductor, Santa

Clara,California,USA

(03/11 to 06/11) 3 Months

o Wrote & Debugged Software on a Teradyne Microflex ATE (IGXL

Environment) to measure LMP 8681(Op Amp) Performance Parameter's

(Offset, Open loop Gain, Output Swing, Short Circuit Current,

Supply Current, CMRR, PSRR), Plot Curve trace & wafer sort

Parameter's using VB.Net

o Usage of Mbayse tool for statistical Analysis.

o Wrote & Debugged Software on Teradyne A510 ATE (Sun SPARC 5, UNIX

based platform) to develop hardware test check routine for

LMV7219(Comparator) using C.

o Bench level Characterization for LMH2200 (PLL) & Op-Amp Using

Signal Generator & Oscilloscope.

. Summer Internship as a Product Engineer at Ikanos Communication,

Fremont, California, USA (06/09 to 08/09) 3 Months.

o Worked on bench characterization for IFE-CO4, IFE-CPE4 chipset

using Spectrum Analyzers, Line Modulator, Signal Generator &

Oscilloscope.

o Performed System Level Testing (SLT) for 5th generation VDSL

product line using automated scripts (UNIX shell & C++ scripts) for

legacy product and documented the results

o Performed ATE and bench correlation. Verified various skew corners

statistical data on ATE. (Teradyne microFlex)

. Electronics Design Engineering Intern at MICROTECH SYSTEMS,

Ahmedabad, GUJARAT, India (01/07 to 11/07)

11 Month's

o Programming on ATMEL (89C51/52) Microcontrollers for various

Measurements application & Stepper Motor Drives.

o Draw Schematic Using ORCAD Schematic Capture tool.

o Designing of LM 555 timer based circuits.

o Design of a DC-DC Converter Based on Requirements.

o Troubleshooting of UPS (Uninterruptible power supply).

o PLC Programming Using RS logix.

Related Coursework:

. Semiconductor Device physics, Linear systems, High-Speed CMOS Design,

Design of CMOS Digital Integrated Circuits, Digital System Design &

Synthesis Using Verilog, Microprocessor/Microcontroller Based System

Design, Radio Frequency Integrated Circuits I & II, Analog Integrated

Circuit, Mixed Signal circuit Design, Selected Topics in Control &

Power Management,, Power Electronics.

Skills:

. Tools: Pspice, ORCAD Schematic Capture, Cadence IC Design Tool

(Virtuoso, VirtuosoXL, Assura DRC/LVS), VCS, Modelsim, MATLAB,

Labview.

. Programming Language's: Assembly Language for 8085/86/88 & 8051,

Verilog, C, C++, Perl.

. Lab Equipments: Oscilloscope, Spectrum Analyzer, Muiltimeter,

Soldering iron, Variac, Logic Analyser

. Communication Protocols: USB,I2C,PCI Express,SPI,RS-232/RS-485

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Projects Undertaken:

. On chip Switched Capacitor DC-DC Converters Using TSMC 0.25 M.

Building a voltage doubler circuit using Cross coupled charged

pump topology. For an input voltage of 2.5 V it gives 4.8 V output for

the switching frequency of 79Mhz.It can handle load up to 47k Ohm and

provides Load current of 100uA.Have successfully done Layout and Post

Extraction of capacitors(using Common centroid method),NMOS,PMOS

transistors Using cadence Virtuso Achieved specification: Power

dissipation 49.67mW, Output ripple voltage 70mV, load of 47k

. Design of a fully Differential Two-Stage Op-amp with common mode

feedback circuit. Used gpdk 090nM CMOS Technology.

First stage is Differential Amplifier, second stage is of Common Gate

Amplifier and Output stage is common Source Amplifier. Designed High

voltage input protection circuit. Performed DC,AC, Transient and

Noise analysis to fully characterize the design. Achieved

Specifications: Open Loop ?3 dB 8.88 MHz, Open Loop Gain 44.28 dB,

Slew rate 0.16nS,Voltage Swing 838mV, Phase Margin 64.4 degree, CMRR

94.19 dB, PSRR 23.45 dB, Offset Voltage 190nV.Throughout Design

cadence Specters is used for Simulation

. Design of a 6 Bit Flash ADC (Analog to Digital Converter). Used gpdk

90nM CMOS technology

Sample and Hold circuit is realized with a switched two-stage single

ended operational amplifier with offset cancellation. Latched

comparators are used in order to increase the speed and sensitivity.

The analog signal was again reconstructed using Verilog based an

encoder. Achieved Specifications: Input Frequency 133 MHz sampling

frequency 500Mhz SNR (Signal to Noise Ratio) 35dB, ENOB (Effective

number of Bits) 5.52, Power consumption 50.73mW, Supply voltage 1V.

For Design Cadence Specters is used for Simulation and Cadence Virtuso

for Layout.

. Design a 3-bit DAC (Digital to Analog Converter) using an R-2R

architecture Used TSMC 0.25uM CMOS technology.

Design of a Single stage Miller Op-Amp with the open loop

3dB gain of 62dB & unity Gain freq. 85Mhz.

Successfully done Layout and Post Extraction of 1k, 2k Resistors and

Miller Op-amp. Measured INL (Integral Nonlinearity), DNL (Differential

Nonlinearity).Achieved Specification: offset error of 2.92uV, Gain

error of 0.224. For Design Simulation Cadence Specters was used and

for Layout Cadence Virtuso.

. Design of Transmitter IF 3-GHz QVCO and PLL (Phase Locked Loop) Using

gpdk 90nM CMOS Technology.

Design of a QVCO(Quadreture Voltage Controlled Oscillator ) with a

tuning rang of 2.7 to 3.3Ghz,Phase Frequency Detector, charge pump,

Bandgap reference Circuit, Loop filter circuit(R=7.6k &

Cap=330pF,41.25pF), 112 divider circuit using verilog A modules.

Achieved Specifications: Signal bandwidth of 800 MHz, IQ amplitude

Mismatch 0 degree, IQ phase mismatch 1.1 degree, RMS Jitter 0.59

degree, Settling time 5 S. For Design Simulation Cadence Specters was

used and for Layout Cadence Virtuso.

. Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell.

Using gpdk 90nm CMOS Technology.

First quadrature RF receiver front end where, in a single stage LNA

(Low noise Amplifier), Mixer, and Voltage Controlled Oscillator (VCO)

shares the same bias current. Achieved specification power

dissipation 2.63mV, Noise figure 3.91 dB, IIP3 -19.16 dB, LNA gain

1.63 dB, Output swing 21.7uV,S11 229 mV at 10Ghz. For Design

Simulation Cadence Specters was used.

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. Design of a 376 MHz 8bit ALU (Arithmetic Logic Unit) using Kogge Stone

Adder. Used AMI06 CMOS Technology.

Two 8 bit data are given as the input to the ALU and another 8 bit

data acts as the control signal which controls the operations to be

performed on the two inputs such as add, subtract, Logic AND, Logic

OR,. Used CMOS Static Logic to Size XOR, AND, OR, D-Flip Flop,

Propagate, Generate blocks. Achieved Specification: Operating

frequency 376 MHz, Power Consumption 16.37mW, layout Area 630 X 370 M

load capacitor value 30fF. For Design Simulation Cadence Specters was

used and for Layout Cadence Virtuso.

. Design of 4 GHZ 24 bit High speed Unsigned Multiplier Circuit using

Wallace Tree architecture. Used IBM 0.13? CMOS Technology.

Use CMOS Domino Logic to size XOR, AND, OR, D-Flip Flop. Design of a

clock tree Driver circuit .Use of a dine size program to size the

transistors. For Design Simulation Cadence Specters was used and for

Layout Cadence Virtuso.

. Design of 8-bit unsigned multiplication circuit using Ripple carry

adder and carry look ahead adder logic using Verilog.

Wrote RTL code for both architectures. Explored the correlation between

area and power vs. delay with Toshiba tc240c and TSMC osu025 libraries. Use

Model-Sim & Synopsys VCS (Verilog Compiler Simulator) for simulation.

Synopsys Design Analyzer tool to synthesize the circuit.

. Design of Temperature controller Using 89C52 Microcontroller and

Interface it with PC.

Display current temperature on LCD & Computer. Accepts set value from user

& Controls temperature up to 150 C. Interface it to computer using RS232

cable. Used IC's are LM 35 Temperature Sensor, MAX 232 for RS232 serial

communication, ADC804 Analog to Digital Converter, 2 lines LCD. An assembly

code is developed for 89C52 Microcontroller for the above task.

. Interfacing of a keypad, Seven Segment & pushbutton to 8086 using DB25

connector.

Goal of this project was to Design hardware and software of a simple

circuit that waits for a push button to be pressed and then scans the

keypad for any key to be pressed and displays pressed key on 7-

segment. If there is no key press, the software just keeps the old

display and continues to scan the keypad. If the key is pressed 6 to 7

times the software stops and wait for to reactivate from the

pushbutton switch. The 7-segment and keypad are connected to standard

PC using parallel port DB 25. An assembly program is developed to scan

the keypad and then display it on 7-segment display.

Extra Curriculum Activity:

. Part of a "SJSU Formula Hybrid" Electrical Engineering Team.

o Has taken a Labview Training from National Instruments on

CompactRio for Data Acquisition application.

. Participated in Roborace Competition Prevoyance2006 at NIRMA

University, Ahmedabad, India.

*Ready to Move any where in USA

*Reference available upon request

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