Engineer Engineering

DEBORAH REKHA JEYASEKAR

**** ******** ****

E-mail:*******.****@*****.***

Irvine CA -92612,

Phone No: 315-***-****

OBJECTIVE:

To seek an exciting and challenging Semiconductor Packaging/Reliability /

Process Engineering position where my experience and knowledge will be

utilized.

SUMMARY:

. Experienced in Fabrication of Biochip - Class 10 and Class 100 clean

room.

. Knowledge/Course work in general Semiconductor fabrication processes,

Photolithography and Photoresist chemistry.

. Selective plasma etch of Si wafer - Hands on experience with LAM2 LRC

Plasma Etcher and wet etch techniques.

. Photolithography- Nikon2205i11D stepper for 8 inch platform and ASML PAS

2400/40 for 6inch platform.

. Operate SSI Model coater and TEL System Clean track ACT8 for coating and

developing wafers.

. Theoretical knowledge in Material characterization techniques such as

EDX, XRD, SEM, TEM.

. Design of Experiments, Statistical Process Control, JMP software.

. Product Packaging Experience: Working knowledge on BGA (Ball Grid Array),

Wafer level BGA packaging technologies, Theoretical knowledge on Flip-Chip

BGA technology.

. Product Reliability Testing and Material Characterization: As a part of

the quality control procedure and to characterize materials that are most

suited for packaging, the following tests were conducted on the final test

vehicles: Dynamic Mechanical Analysis (DMA), Thermal Mechanical Analysis

(TMA),Thermal Cycle Test/Analysis, Drop Test and Tensile Strength Test.

. Active member of a team in the Cluster and Growth site Optimization of 3G

networks for AT-T carrier that involves neighbor list implementation,

coordinating data collecting field engineers, post processing, Coverage

analysis reports & KPI analysis.

. Hands on experience with Mapinfo, Business Objects, TEMS, Agilent, Atoll,

Actix.

EDUCATIONAL BACKGROUND:

Master of Science, Electrical Engineering

(2008-2010)

Specialization: Microelectronics Engineering

Arizona State University, Tempe, AZ.

Bachelor of Engineering, Electronics and Instrumentations Engineering

(2003-2007)

Easwari Engineering College, Anna University, Chennai, India.

RELAVANT COURSEWORK:

Design of Engineering Experiments Dopant Control Technology

IC Packaging

Pattern Transfer Technology Statistical Process

Control Material Characterization Lab

PROFESSIONAL EXPERIENCE:

RF Engineer, Quadgen Wireless Solutions Inc.

Oct 2010 - Mar 2011

RF Engineer, Mobilenet Services Inc.

Mar 2011 - current

Project - Optimization of 3G network for AT-T and T-mobile carrier.

. UMTS Optimization: Implementing neighbors, Troubleshooting RF issues

like Pilot pollution-dominance, link imbalance, PSC Planning, Missing

Neighbors), Idle mode Issues -RRC Setup failures and RAB Set Up. Drive

test analysis, Post processing, call flows studies, Drop calls, handover

process. Parameters tuning, neighbors definition, Design and sites

modifications (Tilt, azimuth, height, etc PS Drops/ Throughput

Analysis, Statistics and KPI's analysis.

Post Processing/ Parameters Tuning: Performed Coverage & interference

analysis (RSCP, and Ec/No), using drive tests and statistical data to

find out any coverage issues like overshooting cells, pilot pollution,

best server signal strength, pilot Ec/No measurements, interference.

Short and long calls initiations during drive tests to find any

Access(missing neighbors), Blocked/Dropped calls and delay/throughput

issues and fixing them.

Tools used: Mapinfo, TEMS, Agilent, Atoll, Actix.

Research Assistant, Bio-Design Institute, Arizona State University

(Oct' 09-June' 10)

Project - Design and Fabrication of Biochip.

. Experienced in bio-microchip device fabrication methods. Attaching

peptides chains on silicon wafers to produce bio-microchips for medical

diagnosis.

. Developed new process using ASML PAS 2400/40 Stepper for 150mm wafers.

. Performed 96 layers of lithography on each wafer.

. Developed and improved process for 200mm wafer using Nikon 2205i11D

stepper.

. Optimized photoresist thickness and measurement using Nano spectrometer.

. Researched on chemically amplified photoresists to improve yield

efficiency.

. Hands on experience with Tokyo Electronics- ACT 8 spin coat and developer

unit.

. Determined yield by measuring fluorescent signal produced by peptide

chains using micro-array scanner and open frame DNA-scope. Trouble-shot

and performed Failure Mode and Effects Analysis (FMEA), Design of

Experiments (DOE) and improved step yield from 78% to 93%

. Strong communication skills and interpersonal relationship with fellow

scientists, wafer fabrication engineering R&D teams.

. Ability to work independently, worked with suppliers for prioritizing

Inventory Needs, oversaw process development, materials selection,

process optimization.

Research Assistant, Microelectronics Products Fabrication,

Testing and (Jan' 08-Jun'08)

Packaging Lab, Arizona

State University

Project - Study the Effect of Mold cap thickness, die attach material,

Solder composition on the Reliability of Lead-free Solder Joints.

. Performed Ball attachment process, Surface mount process and Cross

sectioning for Failure analysis from Cyclic bend tests Thermal Cycle

tests.

. Performed literature search on Pb-free solder joint testing.

. Assisted in performing thermal cycle testing on molded 98CSPs having

varying mold cap thickness and substrate thickness with different SAC

alloys having varying amounts of Ag.

. Performed failure analysis using 3D Keyence microscope to confirm

failure modes.

. Analyzed the results and find out the characteristic life and first

failure of different compositions.

. Made recommendations for further improvements.

SOFTWARE SKILLS:

Operating Systems Windows 98/2000/XP

Application Packages MS Office Suite, SPSS, MATLAB, PSPICE and AutoCAD

Languages C, PHP, PLC

Web Technologies HTML, CSS

Multimedia Tools Adobe Photoshop, Macromedia Flash, Dream weaver 8.0, Adobe

PageMaker, Adobe Astro, Quark Express, Adobe Illustrator,

MS Publisher

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