KENNETH D. SHAW

***** ********* ****, #****

815-***-****

San Diego, CA 92128

abgurn@r.postjobfree.com

PROFESSIONAL PROFILE

Professional experience in the areas of high-speed digital circuit layout

in CMOS and bipolar technologies, mixed signal circuit design and

verification, high-speed memory design, and high frequency RF design.

TECHNICAL SKILLS

Cadence Virtuoso-XL, Opus, Edge, and Silicon Ensemble 5.3, Cell Ensemble,

Chip Assembly Router V11.2.41, Assura DRC/LVS, and Dracula DRC/LVS;

Mentor Calibre DRC /LVS; Synchronicity and ClioSoft EDA systems.

WORK EXPERIENCE

RF Micro Devices, Carlsbad, CA

Senior Mask Layout Designer

01/04/11 - now

Floor planning, new mixed signal and RF analog layout, and reworking

existing layout using Cadence Virtuoso XL. Custom CMOS digital, analog,

mixed signal and high frequency RF layout, requiring common-centrioded,

cross-coupled and inter-digitated matching, differential pair matching,

high frequency net shielding, noise isolation, and meeting current

density and IR drop requirements. Full chip DRC/LVS and taping out

parts. IBM specific three metal and four metal processes.

Qualcomm, San Diego, CA

Contract RF/analog Layout Designer

06/28/10 -

12/28/2010

Floor planning, new mixed signal and RF analog layout, and reworking

existing layout. Custom CMOS digital, analog, mixed signal and high

frequency RF layout, requiring common-centrioded, cross-coupled and inter-

digitated matching, differential pair matching, high frequency net

shielding, noise isolation, and meeting current density and IR drop

requirements. CMOS 65nm technology

Qualcomm, San Diego, CA

Contract RF/analog Layout Designer

09/23/09 -

02/05/2010

Floor planning, new mixed signal and RF layout, reworking existing

layout, generating tiling to meet exacting matching requirements, and top

level verification for tape-out. Custom CMOS digital, analog, mixed

signal and high frequency RF layout, requiring common-centrioded, cross-

coupled and inter-digitated matching, differential pair matching, high

frequency net shielding, noise isolation, and meeting current density and

IR drop requirements.

Kepler: Responsible for creation and management of the bias block, as

well as general layout support for the whole design team. CMOS 65nm

technology

Freescale Semiconductor, Lake Zurich, IL

02/06 - 06/26/09

FSL Layout Design IV

Floor planning, new mixed signal and RF layout, reworking existing

layout, generating tiling to meet exacting matching requirements, and top

level verification for tape-out. Custom CMOS digital, analog, mixed

signal and high frequency RF layout, requiring common-centrioded, cross-

coupled and inter-digitated matching, differential pair matching, high

frequency net shielding, noise isolation, and meeting current density and

IR drop requirements.

IP10W test-chip: test chip in Bi-CMOS 130nm technology, responsible for

BAT-fet drivers, high-precision comparators and the regulator.

Atlas_VLT and AP-ultralite: Power management USB User Interface in Bi_CMOS

130nm technology, responsible for the automatic-lithium-ion-battery-

charger.

Mars: 2G GSM Polarlite AM-PM mixed Transceiver in Mixed-Signal/RF Bi-CMOS

90nm technology; responsible for the tx-dvga, tx-dvga-ladder and low-

harmonic-digital-pad-drivers.

Anaconda_LC, LT and LTE: 2G_3G Transceivers in Mixed-Signal/RF Bi-CMOS

90nm technology; responsible for superfilter-regulator, quadgen-divider,

baseband-filter, baseband-amplifier, bandgap, anatest, LNA-mixer, LNA-tca,

SVGA-bypass-buffer, and crystal-oscillator.

Cmos045 test-chip: test-chip for new Bi-CMOS 45nm technology; responsible

for re-layout of digital reuse cells into the new technology.

Vitesse Semiconductor, Richardson, TX

02/01 - 10/05

Senior Layout Designer

Custom Digital, Analog and Mixed-Signal ASIC design; Using Cadence Virtuoso-

XL for layout and Mentor Calibre for DRC and LVS. Digital auto-place-and-

route using Cadence Silicon Ensemble and Magma Blast Fusion. Full chip

assembly and final full-chip DRC/LVS for tape-out.

Micron Technology, Richardson, TX

06/99 - 02/01

Staff Layout Designer

Custom Digital, Analog and Mixed-Signal IC layout Using Cadence Virtuoso-XL

and Cadence Cell Ensemble for layout, and Dracula for DRC/LVS.

Dallas Semiconductor, Addison, TX

12/95 - 06/99

Layout Designer

Custom Digital, Analog and Mixed-Signal IC layout Using Cadence Opus for

layout, and Dracula for DRC/LVS.

EDUCATION

Bachelor of Arts Degree, Brigham Young University, Provo, UT.

Certificate in Electro-Mechanical Drafting, Idaho State University

Vocational School, Pocatello, ID.

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