Design Manager

Gerald "Woody" Smith II

email: *****@***.***

phone: 408-***-**** Redwood

city, Ca. 94061

Summary of Technical Skills

As an analog engineer I've designed analog components including hearing

aids, battery chargers, LDOs, voltage references, DC-DC converters, DACs

and ADCs( switch cap, Sigma Delta, SAR, pipeline and flash), pressure

sensors, ABS brake systems, filters(switch cap and active), a ton of

Opamps, filters and a variety of analog and digital PLLs.

Design examples- videos

Copy and paste the URL to your browser

digital sigma delta : http://www.youtube.com/watch?v=rP79knhj4Pk

Bandgap design: http://www.youtube.com/watch?v=m0pnIIWNg7U

Previous Experience

ADC LLC/Analog IC Design

. (6/2011-9/15/2011) Bandgap and 60v to 12v sync Buck DC-DDC for LED

driving. VIS .25 BCD process 0.7v output bandgap with 2nd order

curvature correction. Std current mode Buck with integrated Fets-.5A

(2/3/2011-5/15/2011) Sequoia Micro cell design and simulation using

Matlab/Cadence 700V process for AC-DC . Realistically speaking,

Supertex chips with enhancements for AMOLED lighting

(8/1/2010-1/4/2011)SERDES high speed yield enhancement. Working on

VCO(LC) sensitivity-correlating die yield to tuning range and BER

performance. Deep submicron IBM process with extra metal layers

. Developed high efficiency hand-held boost dc-dc converters( 2.5v to

42), high current LED drivers and temp sensors. Also, ADC LLC now has

4 LED driver IP (.35 VIS silicon tested) with Cypress micro based App

board with GUI and USB interface.

. (5/08-3/09) I've been doing power management work for IDT-40v

booster, LDO, temp sensor, 10 ADC. Other recent work included LED

drivers, PWM controller, PLL design and chopper amp based bandgap.

All sim work on Cadence Spectre/Pspice and Matlab

. For 6 months I worked with Leadis Technology developing and completing

a family of LED Driver chips. The technology transfer was complete

11/07. We (Adam Whitworth and myself) developed all of the first

generation Leadis' LED products that you see on their website.

. The previous year, I designed a CDS S&H, photodiode amps,100Mbs 10b

SAR ADC, Bandgap reference and a LDO using Cadence tools including AMS

VHDL.

. Additional work included characterizing 4 TrueCircuits PLL's, crystal

oscillator, I/Os, ESD and signal integrity issues

.

Manager/designer Analog Design

10/03 to 12/05

California Micro Devices

. Job responsibilities include design, group management(6 designers, 2

layout), IP purchase, fab/process selection ( 3 fabs now, 5/6 by years

end) and project management

. During the past year my group introduced 3 new product families with

chips that were sample-able on the first pass. The last was our first

mixed signal chip (LED controller for cell phones) and was a particular

challenge.

The fab was destroyed by the Japanese earthquake and we had to have a

complete resim/ layout, new fab and still meet a promise date for

samples.

. CMD is fabless and competing with firms with lower material costs. We can

only win by using fewer process options and design for high yield in the

highly competitive market for hand-held power management components that

include LDOs, DC-DC switchers, over-current and over-voltage monitors,

power supply sequencers, ESD protection, HDMS and integrated passives

. My personal design work at CMD centered around PLLs, OpAmps(comparators)

and ESD protection(2k-20k

V HBM). Left CMD when the VP of Eng left and the product focus

changed.

Manager/ designer

9/01 to 6/03

IMS-Credence Corp

. Hetrojunction Bipolar(Maxim process) pin driver electronics including a

2GHz variable delay generator.

. Design of 4GHz serial interface transmitter and receiver circuits(SERDES)

in TSMC 0.18u CMOS.

. This included a precision 25-800MHz frequency generator PLL(design); LVDS

transmitters(architecture); over-sampled receivers(arch); and 20 phase

DLL clock generator(design)

. Design work was done using Cadence tools including AMS for mixed mode

simulation and Spectre/HSPICE.

. I also managed the program, a small group of designers, did all

specification development and system architecture

. I also did extensive modeling in MATLAB during the architecture

development.

. Credence had a 14% RIF and I was cut.

Principal Analog Designer

6/00 to 9/01

Embedded Wireless Devices Inc

. Analog circuit design for telephony.

. I was given the system architecture schematics for two designs which I

modeled using MATLAB and was told I needed to have silicon in 9 months.

. I found and bought IP from 3 different companies, found design and layout

resources for the integration

. I designed the PLL, linear regulator, dc-dc converter in UMC's 0.25u

CMOS.

. EWD closed due to a lack of funding

Analog IC Design Consultant

1/ 97 to 6/00

. Specializing in CMOS and bipolar precision, analog signal processing chip

design. Design work included CMOS and bipolar DLLs (20-800Mhz), high

speed Sample and Holds (50-400Mb/s), 60db VGA's, programmable filters

(6th order Bessel 0.05o phase flatness), high speed comparators, switch

cap gain amps and an 10b DAC.

. Switch cap sensor chip with a 2nd order Sigma delta input. After

processing in the application customized DSP the signal was converted

into a 12b ratiometric output using a serial DAC and stored in a sample

and hold SC amplifier valid in both phases. Additional design challenges

on this chip included the developing of an EEprom register bank; merging

the capacitive sensor into the sigma delta to reduce space and power;

operating the chip at 2v while using a new foundry and design rules.

. Another chip in .35u CMOS was an analog low power signal processing chip

that contained 6th order SC bandpass filters and phase linearization,

bandgap, low noise preamp, regulator, triangle waveform generator, SC

absolute value, rectifier and comparator circuits. It all had to work at

2.5V and use less than 2mA's. First silicon met all design goals except

that the bandgap voltage was low, a zero in the bandpass filter was wrong

(parasitic problem) and I should have included an on board buffer for my

test pins. Most work was done on site

Education:

[9/72 TO 6/77] U. of Ill B.S.E.E. and

B.S. Physics

[1/78 to 1/79] U. of AZ. Graduate Studies in Physics and E.E.

[1/80 to 6/82] U. of AZ. M.S.E.E. and advanced studies

[1/87 to 9/91] Penn. State Univ. Doctoral studies

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