Assistant Design

C urriculum Vitae

ALEX MITEV

**** * ******** **** **. Apr 14269, Tucson, AZ 85745

Phone: 520-***-****, 520-***-****

E-mail: *****.****@*****.***,

I NTERESTS

Strong interest and theoretical background in the area of Electronic Design Automation

S ummary

(EDA), including Design for Manufacturability (DFM), Circuit Simulations, Timing Analysis,

Circuit Macromodeling, Device Characterization and Device physics.

Experience in soft-error mitigation techniques of circuits in irradiative environment.

Researched new methods for circuit robustness estimation. Research interest in methods for

circuit radiation hardening.

Experience and scientific interest in circuit compact models, and process variation aware

macromodels. Research in developing models that accurately capture the circuit performance

statistics due to manufacturing variability.

Experience with several Model Order Reduction (MOR) techniques, in applications of timing

analysis. Research in Inversed Regression methods.

Practical experience with linear and nonlinear optimization, numerical methods for

approximation and system identification.

Research work in area of soft computing, including Neural Network applications for system

identification and pattern analysis, Statistical learning such as Support Vector Machine, and

evolutionary algorithms. Interest in Knowledge Engineering and Computational Intelligence .

E DUCATION

U niversity of Arizona, Tucson, USA

Major in Electrical Engineering., Minor in Systems and Industrial Engineering

2 009 - Ph.D.

Dissertation topic: The new VLSI technology challenges in nanometer design scale – the

CGPA 3.4

impact of the high system integrity and process variations

Institute Informational Technologies, Sofia, Bulgaria

(Transferred to UA in 2002)

2 000 - Ph . D .

Major in Computer Engineering.

u nfinished

Dissertation topic: Neural networks with application to system identification and pattern

CGPA 4.0

recognition

Technical University of Sofia, Sofia, Bulgaria

1 996 - M.S. Major in Electrical Engineering.

CGPA 3.8 Master’s thesis: 68020 based versatile microprocessor controller

Technical University of Sofia, Sofia, Bulgaria

1 993 - B.S.

Major in Electrical Engineering.

CGPA 3.4

W ORK E XPERIENCE

Embedded System Developer Strongwatch LLC, T ucson, A Z (contract position)

Worked as an embedded system developer.

2 011

Improved the geo-positioning features of Freedom a multi-sensor surveillance system.

Senior Researcher Aries LLC, Tucson, A Z ( part time position)

Research in the area of Soft Error impact on digital ICs-circuit robustness estimation due to

single and multiple events upsets (SEUs, and MEUs), soft-error mitigation techniques, and

2 009 – 2010

radiation hardening mechanisms for processor cores.

Developed a tool for circuit robustness estimation. Demonstrated two fold of performance

improvement for large scale of circuit design, as compared to related estimation tools.

Contributed several proposals for DoD, DoE, and NASA, including NASA SBIR 2009

topic Reconfigurable VLIW Processor for Software Defined Radio , rewarded with $100k.

Research Assistant Digital VLSI Design Lab – ECE, University of Arizona

Research topic: Device macromodeling f or nanoscale technology circuits .

Developed an advanced compact gate m odel ( AND, OR, INV) for accurate estimation

of t he performance metrics, such as the gate intrinsic delay and power dissipation . The

model i s built upon several distinct points on I - V gate curves (Finite Point (FP)

model ).

Implemented a workflow for studying the proposed model, and extended the variable

2 00 6 – 2009 space to include the transistor manufacturing variability, such as deviation at the

transistor geometry ( L EFF, W EFF, TOX) and threshold voltage mismatch (V TH) .

Improved the proposed model to capture the leakage power, and extended the workflow for

sequential circuits by modeling D flip-flop. Calibration of the FP model, based on comparing

HSPICE simulation results and experimental I-V data.

This position requires programming skills in Verilog-A, Python, Matlab and C++.

Research Assistant SIE, University of Arizona

Worked on a project of Stochastic Linear Programming, and implemented a novel algorithm

for finding the robust solution. The proposed method solves a random linear problem by

2 008

given rating of the optimality and uncertainty of the solution.

Used industry package COIN-OR (C++) and Matlab.

Research Assistant Digital VLSI Design Lab – ECE, University of Arizona

Research topic: Model Order Reduction (MOR) in applications for circuit performance

metrics estimation .

Developed new process variation aware MOR method, for application of circuit

performance function (PF) estimation, such is timing. Demonstrated superior parameter

reducing abilities, as compared to PCA-based approaches.

Implemented two distinct methods: Sliced Inverse Regression method, which requires

2 004 – 2006 parameter sampling to formulate the regression model of the PF, and Principle Hessian

Directions method that by known PF reduces the parameter space by means of pruning

statistical insignificant parameters.

Improved the gate timing modeling by using Probabilistic Collocation Methods and

arbitrary process variation distribution. Calibration and justification the final model with

competitive Monte Carlo simulations in HSPICE. Implemented a tool for fast timing

characterization in C and Matlab

Research Assistant Cancer Center, University of Arizona

Worked in a Bioinformatics lab on project of novel drug discovery for pancreatic cancer.

Responsible for the analysis of microarray genome data. Implemented algorithms for pattern

2 003 – 2004

recognition, and statistical modeling (VBA).

This position requires experience in soft-computing, and programming skills

Research Assistant Institute Information Technologies, Sofia, Bulgaria

1 997 – 2000 Developed neural network applications for pattern recognition and system identification

(Matlab, C). Coauthored on three scientific papers.

C OURSE WORK

Device Electronics, Computer Aided Logic Design, Analog Integrated Circuits, Advanced

G raduate l evel

c ourses Logic Synthesis. Algorithms and Verification, Digital VLSI System Design, Random

Processes in Engineering Application, Stochastic Processes, Fundamentals of Optimization

Theory, Introduction of Machine Learning, Knowledge System Engineering, Engineering

Application of Graph Theory, Data Structures and Algorithms, Data Base Management,

Decision Making Under Uncertainty, Electronic Devices and Circuits, Computer System

and Networks, Fundamentals of Computer Architecture Parallel Computer Systems, Linear

Systems.

U ndergraduate Physics I, Physics II (including Basic of Solid State Physics, and S emiconductor Physics).

l evel courses

C omputer skills P rogramming languages : Matlab, C, C++, Python, Perl, VBA, VB.

E ngineering tools : Cadence Spectre, Berkley Spice, HSPICE, Verilog, Verilog-A, VHDL.

P UBLICATIONS

O. Hafiz, A. Mitev, and J.M. Wang, A Linear Fractional Transform (LFT) Based Model for

J OURNAL

Interconnect Uncertainty, The Institute of Electronics, Information and Communication

A RTICLES

Engineers, Vol. 92A, No. 4 (March 2009), pp. 1148–1160.

J.M. Wang, Y. Cao, C. Min, J. Sun, and A. Mitev, Capturing device mismatch in analog and

mixed-signal designs, IEEE Circuits and Systems Magazine, Vol. 8, No. 4, 2008, pp. 37–44

(Invited paper)

A. Mitev, M. Marefat, D. Ma and J.M. Wang, Principle Hessian Direction Based Parameter

Reduction with Process Variation, IEEE Transactions on VLSI Systems, 2008 (accepted

for publication).

A. Mitev, M. Marefat, D. Ma and J.M. Wang, Parameter Reduction for Variability Analysis

by SIR Method, IEE Proceedings for Circuits, Devices and Systems, IET Circuits, Devices

& Systems, Vol. 2, No. 1 (February 2008), p. 16–22

D. Ganesan, A. Mitev, J.M. Wang, and Y. Cao, Finite-point gate model for fast timing and

C ONFERENCE power analysis, 9th I nternational Symposium on Quality E lectronic Desi gn (ISQED’08), 2008,

P APERS pp. 657–662.

A. Mitev, M. Marefat, D. Ma, and J.M. Wang, Principle Hessian Direction Based Parameter

Reduction with Process Variation , I nternational Conference on Computer - Aided D esign

(ICCAD’07), 2007, pp. 632–637, Best Paper Award Nomination.

A. Mitev, M. Marefat, D. Ma, and J.M. Wang, Principle hessian direction based parameter

reduction for interconnect networks with process variation. S ystem Level Interconnect

P rediction (SLIP’07), 2007, pp. 41–46.

A. Mitev, D. Ganesan, D. Shammgasundaram, Y. Cao, and J.M. Wang, A Robust Finite-

Point Based Gate Model Considering Process Variations , I nternational Conference on

C omputer - Aided Design (ICCAD’07), 2007, pp. 692–697.

A. Mitev, M. Marefat, D. Ma, and J.M. Wang, "Parameter Reduction for Variability Analysis

by Slice Inverse Regression (SIR) Method", A sia and South Pacific Design Automation

C onference (ASPDAC’07), 2007, pp. 468–473.

V. Agarwal, J. Sun, A. Mitev, and J.M. Wang, Delay Uncertainty Reduction by Interconnect

and Gate Splitting , A sia and South Pacific Design Automation Conference (ASPDAC’07), pp.

690–695.

J.M. Wang, A. Mitev, and N. Kankani, Collocation Method based RC/RLC Extraction

with Process Variation , P rogress in Electromagnetic Research Symposi um (PIERS’05),

2005,Hangzhou China.

H ONORS AND AWARDS

The 11th Annual ACM SIGDA Ph.D. Forum/Member Meeting at Design Automation

Conference, DAC-2008, Acceptance rate 30%

Richard Newton Graduate Scholarships Award with Adviser: J. Wang, Design

Automation Conference, DAC-2008

Nominated for Best Paper Award at the International Conference for Computer-Aided

Design ( ICCAD’07 ) 2007

P ROFESSIONAL EXPERIE NCE

REVIEWER FOR

Journal of Electronic Testing

Annals of Mathematics and Artificial Intelligence

Journal of Universal Computer Science

Various conferences including: ASPDAC, ASQED, ISQED, ISCAS, etc.

R EFERENCES

References available upon request

Contact this candidate