Design Engineer

Nirav

**, ****** ***. #***, *** Jose, CA *****

Contact no. 408-***-****; E-mail: *************@*****.***

OBJECTIVE: Seeking a challenging opportunity to enhance career as a Design

and Verification Engineer.

SUMMARY:

. Perform RTL and Gate level simulation and synthesis and functional

Verification.

. Working knowledge of Cadence Virtuoso, Synopsys VCS and Design Vision

(Design Compiler), ModelSim toolsets.

. Strong academic experience of Verification using SystemVerilog.

. Strong in Digital Logic Design

. Experience of Circuit Schematics and Layout Design using Cadence

Tools.

. Excellent coding knowledge in Verilog HDL.

. Strong in Shell scripting.

. Excellent written and verbal communication skills in English.

EDUCATION:

San Jose State University, CA GPA: 3.4/4

MS in Electrical Engineering (Dec 2010)

HNG University, India GPA: 3.6/4

BE in Electronics & Communication (May 07)

TECHNICAL SKILL:

Operating System: Dos, Windows 2000/XP/VISTA/ 7, UNIX, Linux

Hardware description language: Verilog HDL, SystemVerilog

CAD tool: Cadence (Virtuoso), Synopsys (VCS), Synopsys Design Vision,

Modelsim, Xillinx ISE, Quartus II

Tool: Top-view simulator, Multisim (circuit design tool), Ultiboard (PCB

Design Tool)

Programming language: C, C++, Perl, Shell Scripting

Experience:

Intern at Arrow Cad Design Inc (09/11 - current)

. Developed Verilog test-cases for given upcoming Tool

. developed and modified scripts as per requirement

. Develop Test case to verify CAD tool functionality

. Run regression Test

Intern at Twin Antenna (01/07 - 04/07)

. Design and Test an antenna based on provided specification

. Edit the script as per requirement

. Prepare test result documentation

PROJECTS:

AMBA AXI compliant DDR3 Memory controller

Tool: Synopsys VCS, Modelsim; Language: Verilog, SystemVerilog

. Synthesis able AXI compliant DDR3 Controller design.

. Build an internal state machine for DDR3 power-on initialization and

refresh.

. Automatically optimized Read/Write cycle access time according to DDR3

timing specification.

. Easily configured to support different CAS latency and burst length,

by changing the parameters.

. Micron DDR3 Verification IP used to verify controller functionality

. Various test cases develop for verification purpose

. Constraint random based testbench created

. Memory Controller works with 667 MHz DDR3 2-GB Micron Memory

Nirav E-

mail: *************@*****.*** Contact no. 408-***-****

PROJECTS (Continue

Synchronous FIFO design and Verification

Tool: Synopsys VCS; Language: Verilog, SystemVerilog

. Performed RTL coding and Verification in SystemVerilog using VCS.

. Created constraint random based testbench and created Verification

environment.

. Wrote SystemVerilog classes for generator, driver, monitor, and

scoreboard.

. Gathered coverage information to meet the design specification.

2D FIR graphics filter

Tool: Synopsys VCS, ModelSim; Language: Verilog, Shell Scripting

. Designed graphics filter for video enable Cell Phone.

. The video image was 240 columns X 160 rows of pixels (Picture

elements).

. The input and outputs were RGB data. Each Pixel was converted to Y, U

and V. The Y values were filtered, and the resulting YUV data was

converted back to RGB for display purposes.

. The filter was a 5 row X 7 column 2D FIR filter in Verilog Code.

The Analysis of Area-Delay and Power-Delay Trade-offs in Addition Circuits

Tool: Synopsys VCS, Synopsys Design Vision, Modelsim; Language: Verilog,

Shell Scripting

. Area-delay trade-off curves and Power-delay trade-off curves for 8-,

16-, 32-, and 64-bit adders using two libraries, Toshiba and TSMC as

well as two different algorithms (Ripple Carry and CLA).

. Write a RTL verilog code and generated gate level design.

. Run with custom parameter and analysis the Power - Delay and Area-

delay relationship between two algorithms

32 bit address generator using 45nm Technology

Tool: Cadence Virtuoso

. Custom 32-bit address generator using dynamic logic runs at 2 GHz

. It was 5-phase clocking design and latency was 19-phase

. Develop schematic and layout of 32 customs address generator

. Verify functionality by generating various test waveform

. Manual floorplanning, analog extracted view, LVS and DRC checking by

using Cadence CAD tool.

Pipelined ADC (Analog to Digital Converter) Using TSMC 0.18u Technology

Tool: Cadence Virtuoso

. Designed schematic using Cadence CAD tools

. Design works perfectly at 97MHz

. Simulate and prepared layout using TSMC 0.18u Technology

. Run analog extracted to check design as well as DRC and LVS

verification.

COURSE WORK:

. SystemVerilog, High speed CMOS circuit, Digital System Design and

Synthesis, Semiconductor devices, Computer Architecture, ASIC CMOS

Design, Digital Logic Design

Contact this candidate