Engineer Design
Resume:
Noor Md Saleem B
Flat No B-***
Spectra Cypress
Kundalahalli Jn, Maratahalli
Bangalore.
Email: ************@*****.***
Mob : 994-***-****
Total Industrial experience of around 9 years in Verification, Design, RTL
coding and synthesis.
Educational Qualification
B.E. (Electronics & Communication), Bapuji Institute of Technology,
Davanagere
Job Summary
Working as Lead Engineer - Texas Instruments Bangalore from 3rd October
2011 till date
Brought in to the company to Ramp up the new verification team based on my
previous work relation with Texas instruments as a contractor from Wipro
for 6 years.
The Role involves:
. Ramping up the new team on ARM based safety architecture.
. Project and resource planning
. Complete ownership of RTL and Gate level Verification.
. Test bench development
. Test plan creation and reviews
. Improve verification methodologies.
. Interaction with Product engineering and Application teams to
understand and verify the customer used cases.
. Support Product engineering team for silicon Bring up.
. Fault injection methods to verify the safety levels of our
architecture.
. Involved in test time reduction analysis to reduce production cost.
. Flow development for Analog mixed signal simulations and Low power
verification.
. TDL (Tester Designer Language) Generation and simulation.
. Tape out readiness reviews and Risk analysis.
Worked as Project Leader - IC Design at L&T InfoTech Bangalore from 29th
April 2011 till 28th October 2011
Worked with QUALCOMM client through L&T InfoTech.
The Role involved:
. Project and resource planning
. Ownership of Gate level Verification for critical interfaces like HSIC
and DDR.
. Functional vector generation and simulations.
. Silicon support
. Customer interactions and status updates.
Worked as Module Leader at Wipro Technologies Bangalore from 17th October
2005 to 28th April 2011
Worked with Texas Instruments client through Wipro.
The Role involved:
. Test bench development.
. Formal verification.
. Assertions based verification.
. Ownership of RTL and Gate level Verification.
. Functional vector generation and simulations.
. Customer interaction.
. Mentor New team members.
Worked as Associate Engineer at Autotec Systems Bangalore from August 2004
to October 2005
Worked on FPGA based On board microcontrollers.
The Role involved:
. Interaction with Marketing teams to understand the design
requirements.
. Preparation Schematic diagrams.
. RTL coding and verification.
. Board testing.
Technical Summary
Having experience/exposure with various languages/tools
. HDL : Verilog, VHDL
. Simulation Tools : Model-Sim, Synopsys VCS,NCSIM
. Synthesis Tools : DC Shell, Quartus II, XILINX
. Waveform Analyzer : XILINX Chipscope, UnderTow,modelsim & Debussy
. Equivalence Checking : Formality (Synopsys)
. Others : Unix, Vi, Shell scripting, perl
scripting Tcl/Tk, C and Assembly
Language
. Domain Exposure : ARM7, CORTEX R4 architecture, AMBA AXI, AHB
bridges
ETM (Embedded Trace Macrocell), ETB (Embedded Trace
Buffer), Emulation and JTAG protocol
. VLSI DOMAIN/DESIGN SKILLS : ASIC DESIGN, CPLD Design, EMBEDDED, FPGA
DESIGN, Silicon Characterization & Debug
PROJECTS SUMMARY:
1. Conqueror SOC
|Description |This SOC is designed for Safety applications |
| |in Automotive and industrial domains.Cortex R5|
| |based SOC. |
|Role |Verification lead |
|Operating |Unix |
|System(s) | |
|Skills |Perl, Clear Case,,Citrix MetaFrame |
| |Presentation Server,ASIC |
| |DESIGN,EMBEDDED,Embedded Systems |
|Environment |Synopsys VCS,Modelsim, Verilog, Vera,C |
|Contribution |Worked on System Level verification of |
| |critical blocks like DMA, Core sight etc. |
| |RTL Simulations |
| |Gate Level Simulations With and Without Timing|
| | |
| |Functional Vector Generation |
| |Team Management |
|Start Date |03/10/2011 |
|End Date |Till Date |
|Team Size |8 |
|Company | Texas Instruments Bangalore |
2. Waverider SOC
|Description |This SOC is designed for Qualcomm for CDMA |
| |mobile applications |
|Role |Project Lead |
|Operating |Unix |
|System(s) | |
|Skills |Perl,Clear Case,,Citrix MetaFrame Presentation|
| |Server,ASIC DESIGN,EMBEDDED,Embedded Systems |
|Environment |Synopsys VCS,Modelsim, Verilog, Vera,C |
|Contribution |Worked on System Level verification of |
| |critical blocks like TSIF,HSIC and EBI(DDR). |
| |Gate Level Simulations With and Without Timing|
| | |
| |Functional Vector Generation |
| |Client Interaction and Status Updates |
| |Team Management |
|Start Date |29/04/2011 |
|End Date |24/10/2011 |
|Period |6 months |
|Team Size |8 |
|Company | L & T Infotech, Bangalore |
3. Hermes ASIC
|Description |This ASIC is designed for Texas Instruments |
| |India as client.End client would be Ericcson. |
|Role |Module Leader |
|Operating |Unix |
|System(s) | |
|Skills |Perl,Clear Case,Finite State Machines |
| |(FSM),Citrix MetaFrame Presentation |
| |Server,ASIC DESIGN,EMBEDDED,Embedded Systems |
|Environment |Synopsys VCS, Verilog, System verilog,C |
|Contribution |Worked on System Level verification of |
| |critical blocks like CCR,AVS and PLB2OCP |
| |Bridge. |
| |Gate Level Simulations With and Without Timing|
| | |
| |Client Interaction and Status Updates |
| |Team Management |
|Start Date |02/09/2010 |
|End Date |15/04/2011 |
|Period |7 Months |
|Team Size |6 |
|Company | Wipro Technologies |
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4. Puma SOC
|Description |This SOC is designed for Texas Instruments |
| |India as client.End client would be Ericcson |
| |Molndal. |
|Role |Module Leader |
|Operating |Unix |
|System(s) | |
|Skills |Perl,Clear Case,Finite State Machines |
| |(FSM),Citrix MetaFrame Presentation |
| |Server,ASIC DESIGN,EMBEDDED,Embedded Systems |
|Environment |Synopsys VCS, Verilog, System verilog,C |
|Contribution |Worked on System Level verification DDR and |
| |EBCO Interface. |
| |Gate Level Simulations With and Without Timing|
| | |
| |Client Interaction and Status Updates |
| |Team Management |
|Start Date |02/10/2010 |
|End Date |25/02/2011 |
|Period |4 Months |
|Team Size |3 |
|Company | Wipro Technologies |
5. MTC80 Testchip
|Description |MTC80 is a memory testchi for Texas |
| |Instruments India as client. |
|Role |Module Leader |
|Operating |Unix |
|System(s) | |
|Skills |Perl,Clear Case,Finite State Machines |
| |(FSM),Citrix MetaFrame Presentation |
| |Server,ASIC DESIGN,EMBEDDED,Embedded Systems |
|Environment |Synopsys VCS, Verilog, System verilog |
|Contribution |I had taken the ownership of entire |
| |verification activity and design activity for |
| |some critical blocks clkgen, data path etc. |
| |Top level testbench in verilog. Involved in |
| |both RTL simulations and GLS with timing. Had |
| |taken the ownership of TDL generation and |
| |simulations. |
|Start Date |01/05/2010 |
|End Date |03/08/2010 |
|Period |3 Months |
|Team Size |3 |
|Company | Wipro Technologies |
6. DDR70 Testchip
|Description |DDR70 testchip is designed as a DDR PHY for |
| |Kayton SOC for Texas Instruments India as |
| |client. |
|Role |Module Leader |
|Operating |Unix |
|System(s) | |
|Skills |Perl,Clear Case,Finite State Machines |
| |(FSM),Citrix MetaFrame Presentation |
| |Server,ASIC DESIGN,EMBEDDED,Embedded Systems |
|Environment |Synopsys VCS, Verilog, System verilog |
|Contribution |I had taken the ownership of entire |
| |verification activity and design activity for |
| |some critical blocks as Data Path and FIFO for|
| |Data and Command Macros of DDR PHY. |
| |DDR Macros were verified using System Verilog |
| |testcases.Top level testbench in verilog. |
|Start Date |02/12/2009 |
|End Date |07/05/2010 |
|Period |6 Months |
|Team Size |5 |
|Company | Wipro Technologies |
7. MTC73 Testchip
|Description |MTC73 is a memory testchip with different TI |
| |memories integrated into the architecture. |
|Role |Module Leader |
|Operating |Unix |
|System(s) | |
|Skills |Perl,Clear Case,Finite State Machines |
| |(FSM),Citrix MetaFrame Presentation Server,ASIC|
| |DESIGN,EMBEDDED,Embedded Systems |
|Environment |Synopsys VCS, Verilog |
|Contribution |I had taken the ownership of entire |
| |verification activity. |
| |Verification process involves unit level |
| |verification of critical modules like clock |
| |generator, configuration registers block and |
| |memory subchips.The top level testbench is |
| |coded in verilog.The memory testchip had to be |
| |tested in different modes using different |
| |algorithms like march13,march09,checkerboard |
| |and wrenz.I had also taken the ownership of TDL|
| |generation using perl scripting. |
| |Hook-Up checks were done using TCL scripts. |
| |Algorithms were buit in verilog. |
|Start Date |Feb 2009 |
|End Date |August 2009 |
|Period |6 |
|Team Size |5 |
|Company | Wipro Technologies |
8. RFCODEC Analog Modelling and Power Validation
|Description |Analog Models are used with the digital blocks |
| |during mixed signal simulations.These models |
| |were developed for Texas Instruments Dallas, |
| |Texas USA |
|Role |Module Leader |
|Operating |Unix |
|System(s) | |
|Skills |Perl, Analog Modelling tools like VERSE,Power |
| |Analysys tool PrimePower and Power Theater |
|Environment |Modelsim |
|Contribution |I had Taken the ownership of Analog Modelling |
| |for various rfcodecs like Kylie,VDAC etc. |
| |I was also involved in the power analysis of |
| |Various digital blocks of these rfcodecs.The |
| |RTL power analysis was done using sequence |
| |Power Theater tool and gate level power |
| |analysis was done using synopsys Prime power |
|Start Date |Feb 2008 |
|End Date |Sep 2008 |
|Period |7 |
|Team Size |3 |
|Company | Wipro Technologies |
9. TI_AEC_MIRAP
|Description |MIRAP is an SOC designed for BOSCH as |
| |customer.It finds its end application in |
| |Automotives |
|Role |Project Engineer |
|Operating |Linux,Sun Solaris,Unix |
|System(s) | |
|Skills |Assembly Language,Clear Case,Finite State |
| |Machines (FSM),Citrix MetaFrame Presentation|
| |Server,ASIC DESIGN,EMBEDDED,Embedded Systems|
|Environment |Modelsim |
|Contribution |I had taken the ownership in the critical |
| |modules like CORESIGHT and LIN.I am |
| |responsible for the synthesis, RTL |
| |simulations and gate level simulations with |
| |SDF.I have found many critical bugs in my |
| |modules and also the bridges which were |
| |appriciated by the customer. |
|Start Date |20/12/2006 |
|End Date |24/11/2007 |
|Period |10 |
|Team Size |8 |
|Other | |
|Information | |
10.TI_AEC_MIRA
|Description |MIRA is an CORTEX R4 based SOC for ABS |
| |application |
|Role |Project Engineer |
|Operating |Linux |
|System(s) | |
|Skills |Assembly Language,Clear Case,Finite State |
| |Machines (FSM),Citrix MetaFrame Presentation|
| |Server,ASIC DESIGN,EMBEDDED,Embedded Systems|
|Environment |Linux, Solaris |
|Contribution |Handling following modules of MIRA 1. DMA 2.|
| |ESRAM Wrapper 3. MCRC Responsible for RTL |
| |and netlist simulations for the above |
| |modules. |
|Start Date |05/04/2006 |
|End Date |03/09/2006 |
|Period |5 |
|Team Size |11 |
|Company | Wipro Technologies |
11. HP BOBA ASIC
|Description |BOBA ASIC consists of several blocks like |
| |DELTA,MOVE,CCPI,UMAC etc.The Blocks focused |
| |by me were DELTA and MOVE. DELTA Block |
| |consists Compression and Decompression |
| |logic, Two MDMA's and AXI Interface. The |
| |Functionality of DELTA Block is to read the |
| |data from the memory Compress/Decompress the|
| |data and put back to the memory. The Boba |
| |Move block is simply 2 Modular DMA (MDMA) |
| |units placed back-to-back. One MDMA is |
| |dedicated to input and one dedicated to |
| |output. |
|Role |Project Engineer |
|Operating |RT-Linux |
|System(s) | |
|Skills |PERL,Clear Case,Mentor,ASIC DESIGN,Embedded |
| |Systems |
|Environment |Modelsim, Linux |
|Contribution |Responsible for Verification of DELTA and |
| |MOVE Blocks. |
|Start Date |24/10/2005 |
|End Date |10/02/2006 |
|Period |3 |
|Team Size |3 |
|Company | Wipro Technologies |
12. FPGA Design for On Board Memory Module
|Description |On Board Memory module was designed for NSTL|
| |( Naval Science & Technological Lab) Vizag |
| |for their Data Acquisition Applications. The|
| |task is to store the data acquired into an |
| |on board memory of 8 GB. FPGA design |
| |consists of a Nand Flash Controller, |
| |Microcontroller AM18CU interface, read and |
| |write control for the FIFOs etc. |
|Role |Project Engineer |
|Operating |Windows 2000 |
|System(s) | |
|Skills |ASIC / FPGA,Finite State Machines |
| |(FSM),Mentor,CPLD Design,EMBEDDED,FPGA |
| |DESIGN,Embedded Systems |
|Environment |VHDL,Altera Quartus, Modelsim. |
|Contribution |Responsible to write code in VHDL for Nand |
| |Flash Controller,FIFO interface, Processor |
| |interface etc. Synthesis, simulation, |
| |Implementation and STA. Involved in Board |
| |level implementation and Debugging |
|Start Date |07/02/2005 |
|End Date |09/09/2005 |
|Period |6 |
|Team Size |2 |
|Company |Autotec Systems Pvt Ltd |
13. CPLD Design for On Board Processor
|Description |On Board Processor was designed for DRDL |
| |Hyderabad The Module works as an On Board |
| |Processor for AKASH Missile. The unit is |
| |responsible for communication with |
| |interfaces like Telemetry and CGU (Command |
| |Guidance Unit). The CPLD Design consists of |
| |the control logic for CGU and Telemetry |
| |interfaces, ADC and DAC Interfaces. |
|Role |Project Engineer |
|Operating |Windows 2000 |
|System(s) | |
|Skills |ASIC / FPGA,CPLD Design,EMBEDDED,FPGA |
| |DESIGN,Embedded Systems |
|Environment |VHDL,Cypress, Modelsim |
|Contribution |Responsible for entire CPLD design. Board |
| |level integration and debugging. Proved the |
| |functionality with the actual CGU and |
| |Telemetry interface. |
|Start Date |08/09/2004 |
|End Date |28/01/2005 |
|Period |3 |
|Team Size |2 |
|Company | Autotec Systems Pvt Ltd |
Personal Details
|Date Of |22 Jul 1978 |
|Birth | |
|Father |B Meheboob |
|Mother |M Zareena |
|Nationality |Indian |
|Religion |Muslim |
|Marital |Married |
|Status | |
|Visa Status |Buisness Visa - USA Valid till 2018 |
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