Project Engineering

REKHA.D

Mobile: +91-960**-*****, E Mail: ***************@*****.***

Address: NO-17D/12 Chetti Kulam, N G O Nagar, Kanchipuram-631502, Tamil

Nadu

Objective

To work in a challenging, competitive and mentally stimulating

environment so as to harness my potential in a Way to give in the best of

my capabilities.

Education

. M.E., VLSI Design (July 2012)

SKR Engineering College

Anna University.

Percentage: 7.24 CGPA (first class)

. B.E Electronics & Communication Engineering (April 2010)

Arulmigu Meenakshi Amman College of Engineering

Anna University.

Percentage: 71 (first class)

. Diploma in Electronics & communication Engineering (April 2007)

Bakthavatsalam polytechnic

Directorate of Technical Education.

Percentage: 88 (first class)

. Secondary Education (April 2004)

S.S.K.V Higher Secondary School

State Board.

Percentage: 68.60

Technical Exposure

| | |

|Area of Interest : VLSI design, Digital electronics | |

|Programming Language : C, Verilog, Vhdl | |

|Simulation Tools : ModelSim,Xilinx | |

|Operating System : Windows | |

|Project Description |

ME PROJECT :

Project Title : Implementation of BCD Adder Optimizing Quantum Cost

Based on a

New Reversible Gate.

Functional Description :

Reversible logic is one of the Emerging Technologies having

Promising Application in Quantum Computing .The 4 Bit Reversible Binary

Adder to add the BCD number and Finally the Conversion of the Binary

result to the BCD format using a Reversible Binary to BCD converter.

BE PROJECT :

Project Title : A Hierarchical Approach for Modelling an MPLS Network

Using Verilog.

Functional Description :

MPLS is a protocol framework used primarily to prioritize

internet traffic and it offers a better performance and flexibility than

IP routing. MPLS performance can be enhanced by executing core tasks in

hardware while allowing other tasks to be executed in software to guard

against performance degradation. Ingress LER assigns a label to the IP

packet header, which then used by LSR to switch the packet and forward it

to the egress LER by changing the label depending on the destination of

the packet.

DIPLOMA PROJECT:

Project Title : Cyber X Force - SMS Alert System.

Functional Description :

It is a commercial software which is used to intimate the cyber

crime to police through SMS. Used for tracing sender who sends threat mail

anonymous person.

|Co-Curricular Activities: |

. Presented a paper titled, "Digital Image watermarking by DWT-DCT

method" in 2nd National Conference at SKR Engineering College,

Chennai.

. Completed Five day Workshop on "Hands on session using Lab VIEW" at SKR

Engineering College, Chennai.

. Completed Five day Workshop on "Lab VIEW data acquisition and its

application" at SKR Engineering College, Chennai.

|Extra Curricular Activities |

. Completed VLSI DESIGN -Front End Course, In Verilog Course Team.

|pROFesSIONAL EXPERIENCE IN COURSE TIME |

1. TWO WIRE SERIAL EEPROM

This project provides 1024 bits of serial electrically erasable and

programmable read only memory (EEPROM) organized as 128 words of 8 bits

each. The device is optimized for use in many industrial and commercial

applications where low power and low voltage operation are essential.

It is accessed via a two-wire serial interface.

Responsibility

. Involved in creating a module for Control Logic Block to get the

address and to write the data into memory.

. FSM Design.

2. USB EMBEDDED CLOCKING

In an USB based system the clock is extracted from the

data. Synthesizable embedded clocking used for embed the clock signal

along with the serial data line. It used for physical layer of serial

communication devices. It has the simple logic like FIFO, data pattern

detector and multiplexer.

Responsibility

. Requirement study analysis.

. Logic Implementation in RTL.

3. GENERIC FIFO, GENERIC COUNTER, GENERIC MULTIPLEXER

. Designed and Verified Generic, reusable RTL models such as FIFO,

Counter and Multiplexer

. Designed FIFO to be configurable as Synchronous or Asynchronous

| Personal Information |

Father name : Mr.T.N.Dayalan

Date of Birth : 07/03/1988

Sex : Female

Nationality : Indian

Religion : Hindu

Marital Status : Single

Languages Known : Tamil, English

Passport Details : NO : H4938768, Date Of Expiry

: 09/11/2019

I certify that the information given above is true, complete and correct to

the best of my knowledge and belief.

REKHA.D

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